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1.. SPDX-License-Identifier: GPL-2.0
2
3===========================
4AMD64 Specific Boot Options
5===========================
6
7There are many others (usually documented in driver documentation), but
8only the AMD64 specific ones are listed here.
9
10Machine check
11=============
12Please see Documentation/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
13
14   mce=off
15		Disable machine check
16   mce=no_cmci
17		Disable CMCI(Corrected Machine Check Interrupt) that
18		Intel processor supports.  Usually this disablement is
19		not recommended, but it might be handy if your hardware
20		is misbehaving.
21		Note that you'll get more problems without CMCI than with
22		due to the shared banks, i.e. you might get duplicated
23		error logs.
24   mce=dont_log_ce
25		Don't make logs for corrected errors.  All events reported
26		as corrected are silently cleared by OS.
27		This option will be useful if you have no interest in any
28		of corrected errors.
29   mce=ignore_ce
30		Disable features for corrected errors, e.g. polling timer
31		and CMCI.  All events reported as corrected are not cleared
32		by OS and remained in its error banks.
33		Usually this disablement is not recommended, however if
34		there is an agent checking/clearing corrected errors
35		(e.g. BIOS or hardware monitoring applications), conflicting
36		with OS's error handling, and you cannot deactivate the agent,
37		then this option will be a help.
38   mce=no_lmce
39		Do not opt-in to Local MCE delivery. Use legacy method
40		to broadcast MCEs.
41   mce=bootlog
42		Enable logging of machine checks left over from booting.
43		Disabled by default on AMD Fam10h and older because some BIOS
44		leave bogus ones.
45		If your BIOS doesn't do that it's a good idea to enable though
46		to make sure you log even machine check events that result
47		in a reboot. On Intel systems it is enabled by default.
48   mce=nobootlog
49		Disable boot machine check logging.
50   mce=tolerancelevel[,monarchtimeout] (number,number)
51		tolerance levels:
52		0: always panic on uncorrected errors, log corrected errors
53		1: panic or SIGBUS on uncorrected errors, log corrected errors
54		2: SIGBUS or log uncorrected errors, log corrected errors
55		3: never panic or SIGBUS, log all errors (for testing only)
56		Default is 1
57		Can be also set using sysfs which is preferable.
58		monarchtimeout:
59		Sets the time in us to wait for other CPUs on machine checks. 0
60		to disable.
61   mce=bios_cmci_threshold
62		Don't overwrite the bios-set CMCI threshold. This boot option
63		prevents Linux from overwriting the CMCI threshold set by the
64		bios. Without this option, Linux always sets the CMCI
65		threshold to 1. Enabling this may make memory predictive failure
66		analysis less effective if the bios sets thresholds for memory
67		errors since we will not see details for all errors.
68   mce=recovery
69		Force-enable recoverable machine check code paths
70
71   nomce (for compatibility with i386)
72		same as mce=off
73
74   Everything else is in sysfs now.
75
76APICs
77=====
78
79   apic
80	Use IO-APIC. Default
81
82   noapic
83	Don't use the IO-APIC.
84
85   disableapic
86	Don't use the local APIC
87
88   nolapic
89     Don't use the local APIC (alias for i386 compatibility)
90
91   pirq=...
92	See Documentation/x86/i386/IO-APIC.rst
93
94   noapictimer
95	Don't set up the APIC timer
96
97   no_timer_check
98	Don't check the IO-APIC timer. This can work around
99	problems with incorrect timer initialization on some boards.
100
101   apicpmtimer
102	Do APIC timer calibration using the pmtimer. Implies
103	apicmaintimer. Useful when your PIT timer is totally broken.
104
105Timing
106======
107
108  notsc
109    Deprecated, use tsc=unstable instead.
110
111  nohpet
112    Don't use the HPET timer.
113
114Idle loop
115=========
116
117  idle=poll
118    Don't do power saving in the idle loop using HLT, but poll for rescheduling
119    event. This will make the CPUs eat a lot more power, but may be useful
120    to get slightly better performance in multiprocessor benchmarks. It also
121    makes some profiling using performance counters more accurate.
122    Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
123    CPUs) this option has no performance advantage over the normal idle loop.
124    It may also interact badly with hyperthreading.
125
126Rebooting
127=========
128
129   reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] [, [w]arm | [c]old]
130      bios
131        Use the CPU reboot vector for warm reset
132      warm
133        Don't set the cold reboot flag
134      cold
135        Set the cold reboot flag
136      triple
137        Force a triple fault (init)
138      kbd
139        Use the keyboard controller. cold reset (default)
140      acpi
141        Use the ACPI RESET_REG in the FADT. If ACPI is not configured or
142        the ACPI reset does not work, the reboot path attempts the reset
143        using the keyboard controller.
144      efi
145        Use efi reset_system runtime service. If EFI is not configured or
146        the EFI reset does not work, the reboot path attempts the reset using
147        the keyboard controller.
148
149   Using warm reset will be much faster especially on big memory
150   systems because the BIOS will not go through the memory check.
151   Disadvantage is that not all hardware will be completely reinitialized
152   on reboot so there may be boot problems on some systems.
153
154   reboot=force
155     Don't stop other CPUs on reboot. This can make reboot more reliable
156     in some cases.
157
158Non Executable Mappings
159=======================
160
161  noexec=on|off
162    on
163      Enable(default)
164    off
165      Disable
166
167NUMA
168====
169
170  numa=off
171    Only set up a single NUMA node spanning all memory.
172
173  numa=noacpi
174    Don't parse the SRAT table for NUMA setup
175
176  numa=nohmat
177    Don't parse the HMAT table for NUMA setup, or soft-reserved memory
178    partitioning.
179
180  numa=fake=<size>[MG]
181    If given as a memory unit, fills all system RAM with nodes of
182    size interleaved over physical nodes.
183
184  numa=fake=<N>
185    If given as an integer, fills all system RAM with N fake nodes
186    interleaved over physical nodes.
187
188  numa=fake=<N>U
189    If given as an integer followed by 'U', it will divide each
190    physical node into N emulated nodes.
191
192ACPI
193====
194
195  acpi=off
196    Don't enable ACPI
197  acpi=ht
198    Use ACPI boot table parsing, but don't enable ACPI interpreter
199  acpi=force
200    Force ACPI on (currently not needed)
201  acpi=strict
202    Disable out of spec ACPI workarounds.
203  acpi_sci={edge,level,high,low}
204    Set up ACPI SCI interrupt.
205  acpi=noirq
206    Don't route interrupts
207  acpi=nocmcff
208    Disable firmware first mode for corrected errors. This
209    disables parsing the HEST CMC error source to check if
210    firmware has set the FF flag. This may result in
211    duplicate corrected error reports.
212
213PCI
214===
215
216  pci=off
217    Don't use PCI
218  pci=conf1
219    Use conf1 access.
220  pci=conf2
221    Use conf2 access.
222  pci=rom
223    Assign ROMs.
224  pci=assign-busses
225    Assign busses
226  pci=irqmask=MASK
227    Set PCI interrupt mask to MASK
228  pci=lastbus=NUMBER
229    Scan up to NUMBER busses, no matter what the mptable says.
230  pci=noacpi
231    Don't use ACPI to set up PCI interrupt routing.
232
233IOMMU (input/output memory management unit)
234===========================================
235Multiple x86-64 PCI-DMA mapping implementations exist, for example:
236
237   1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all
238      (e.g. because you have < 3 GB memory).
239      Kernel boot message: "PCI-DMA: Disabling IOMMU"
240
241   2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
242      Kernel boot message: "PCI-DMA: using GART IOMMU"
243
244   3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
245      e.g. if there is no hardware IOMMU in the system and it is need because
246      you have >3GB memory or told the kernel to us it (iommu=soft))
247      Kernel boot message: "PCI-DMA: Using software bounce buffering
248      for IO (SWIOTLB)"
249
250   4. <arch/x86_64/pci-calgary.c> : IBM Calgary hardware IOMMU. Used in IBM
251      pSeries and xSeries servers. This hardware IOMMU supports DMA address
252      mapping with memory protection, etc.
253      Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
254
255::
256
257  iommu=[<size>][,noagp][,off][,force][,noforce]
258  [,memaper[=<order>]][,merge][,fullflush][,nomerge]
259  [,noaperture][,calgary]
260
261General iommu options:
262
263    off
264      Don't initialize and use any kind of IOMMU.
265    noforce
266      Don't force hardware IOMMU usage when it is not needed. (default).
267    force
268      Force the use of the hardware IOMMU even when it is
269      not actually needed (e.g. because < 3 GB memory).
270    soft
271      Use software bounce buffering (SWIOTLB) (default for
272      Intel machines). This can be used to prevent the usage
273      of an available hardware IOMMU.
274
275iommu options only relevant to the AMD GART hardware IOMMU:
276
277    <size>
278      Set the size of the remapping area in bytes.
279    allowed
280      Overwrite iommu off workarounds for specific chipsets.
281    fullflush
282      Flush IOMMU on each allocation (default).
283    nofullflush
284      Don't use IOMMU fullflush.
285    memaper[=<order>]
286      Allocate an own aperture over RAM with size 32MB<<order.
287      (default: order=1, i.e. 64MB)
288    merge
289      Do scatter-gather (SG) merging. Implies "force" (experimental).
290    nomerge
291      Don't do scatter-gather (SG) merging.
292    noaperture
293      Ask the IOMMU not to touch the aperture for AGP.
294    noagp
295      Don't initialize the AGP driver and use full aperture.
296    panic
297      Always panic when IOMMU overflows.
298    calgary
299      Use the Calgary IOMMU if it is available
300
301iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
302implementation:
303
304    swiotlb=<pages>[,force]
305      <pages>
306        Prereserve that many 128K pages for the software IO bounce buffering.
307      force
308        Force all IO through the software TLB.
309
310Settings for the IBM Calgary hardware IOMMU currently found in IBM
311pSeries and xSeries machines
312
313    calgary=[64k,128k,256k,512k,1M,2M,4M,8M]
314      Set the size of each PCI slot's translation table when using the
315      Calgary IOMMU. This is the size of the translation table itself
316      in main memory. The smallest table, 64k, covers an IO space of
317      32MB; the largest, 8MB table, can cover an IO space of 4GB.
318      Normally the kernel will make the right choice by itself.
319    calgary=[translate_empty_slots]
320      Enable translation even on slots that have no devices attached to
321      them, in case a device will be hotplugged in the future.
322    calgary=[disable=<PCI bus number>]
323      Disable translation on a given PHB. For
324      example, the built-in graphics adapter resides on the first bridge
325      (PCI bus number 0); if translation (isolation) is enabled on this
326      bridge, X servers that access the hardware directly from user
327      space might stop working. Use this option if you have devices that
328      are accessed from userspace directly on some PCI host bridge.
329    panic
330      Always panic when IOMMU overflows
331
332
333Miscellaneous
334=============
335
336  nogbpages
337    Do not use GB pages for kernel direct mappings.
338  gbpages
339    Use GB pages for kernel direct mappings.
340