1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 nand = &gpmi; 17 ssi0 = &ssi1; 18 usb0 = &usbh1; 19 usb1 = &usbotg; 20 }; 21 22 chosen { 23 bootargs = "console=ttymxc1,115200"; 24 }; 25 26 backlight { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm4 0 5000000>; 29 brightness-levels = <0 4 8 16 32 64 128 255>; 30 default-brightness-level = <7>; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 user-pb { 39 label = "user_pb"; 40 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 41 linux,code = <BTN_0>; 42 }; 43 44 user-pb1x { 45 label = "user_pb1x"; 46 linux,code = <BTN_1>; 47 interrupt-parent = <&gsc>; 48 interrupts = <0>; 49 }; 50 51 key-erased { 52 label = "key-erased"; 53 linux,code = <BTN_2>; 54 interrupt-parent = <&gsc>; 55 interrupts = <1>; 56 }; 57 58 eeprom-wp { 59 label = "eeprom_wp"; 60 linux,code = <BTN_3>; 61 interrupt-parent = <&gsc>; 62 interrupts = <2>; 63 }; 64 65 tamper { 66 label = "tamper"; 67 linux,code = <BTN_4>; 68 interrupt-parent = <&gsc>; 69 interrupts = <5>; 70 }; 71 72 switch-hold { 73 label = "switch_hold"; 74 linux,code = <BTN_5>; 75 interrupt-parent = <&gsc>; 76 interrupts = <7>; 77 }; 78 }; 79 80 leds { 81 compatible = "gpio-leds"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_gpio_leds>; 84 85 led0: user1 { 86 label = "user1"; 87 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 88 default-state = "on"; 89 linux,default-trigger = "heartbeat"; 90 }; 91 92 led1: user2 { 93 label = "user2"; 94 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 95 default-state = "off"; 96 }; 97 98 led2: user3 { 99 label = "user3"; 100 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 101 default-state = "off"; 102 }; 103 }; 104 105 memory@10000000 { 106 device_type = "memory"; 107 reg = <0x10000000 0x40000000>; 108 }; 109 110 pps { 111 compatible = "pps-gpio"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_pps>; 114 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 115 status = "okay"; 116 }; 117 118 reg_1p0v: regulator-1p0v { 119 compatible = "regulator-fixed"; 120 regulator-name = "1P0V"; 121 regulator-min-microvolt = <1000000>; 122 regulator-max-microvolt = <1000000>; 123 regulator-always-on; 124 }; 125 126 reg_3p3v: regulator-3p3v { 127 compatible = "regulator-fixed"; 128 regulator-name = "3P3V"; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 regulator-always-on; 132 }; 133 134 reg_usb_h1_vbus: regulator-usb-h1-vbus { 135 compatible = "regulator-fixed"; 136 regulator-name = "usb_h1_vbus"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 regulator-always-on; 140 }; 141 142 reg_usb_otg_vbus: regulator-usb-otg-vbus { 143 compatible = "regulator-fixed"; 144 regulator-name = "usb_otg_vbus"; 145 regulator-min-microvolt = <5000000>; 146 regulator-max-microvolt = <5000000>; 147 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 148 enable-active-high; 149 }; 150 151 sound { 152 compatible = "fsl,imx6q-ventana-sgtl5000", 153 "fsl,imx-audio-sgtl5000"; 154 model = "sgtl5000-audio"; 155 ssi-controller = <&ssi1>; 156 audio-codec = <&codec>; 157 audio-routing = 158 "MIC_IN", "Mic Jack", 159 "Mic Jack", "Mic Bias", 160 "Headphone Jack", "HP_OUT"; 161 mux-int-port = <1>; 162 mux-ext-port = <4>; 163 }; 164}; 165 166&audmux { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_audmux>; 169 status = "okay"; 170}; 171 172&can1 { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_flexcan1>; 175 status = "okay"; 176}; 177 178&clks { 179 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 180 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 181 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 182 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 183}; 184 185&fec { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_enet>; 188 phy-mode = "rgmii-id"; 189 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 190 status = "okay"; 191}; 192 193&gpmi { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_gpmi_nand>; 196 status = "okay"; 197}; 198 199&hdmi { 200 ddc-i2c-bus = <&i2c3>; 201 status = "okay"; 202}; 203 204&i2c1 { 205 clock-frequency = <100000>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_i2c1>; 208 status = "okay"; 209 210 gsc: gsc@20 { 211 compatible = "gw,gsc"; 212 reg = <0x20>; 213 interrupt-parent = <&gpio1>; 214 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 215 interrupt-controller; 216 #interrupt-cells = <1>; 217 #size-cells = <0>; 218 219 adc { 220 compatible = "gw,gsc-adc"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 channel@0 { 225 gw,mode = <0>; 226 reg = <0x00>; 227 label = "temp"; 228 }; 229 230 channel@2 { 231 gw,mode = <1>; 232 reg = <0x02>; 233 label = "vdd_vin"; 234 }; 235 236 channel@5 { 237 gw,mode = <1>; 238 reg = <0x05>; 239 label = "vdd_3p3"; 240 }; 241 242 channel@8 { 243 gw,mode = <1>; 244 reg = <0x08>; 245 label = "vdd_bat"; 246 }; 247 248 channel@b { 249 gw,mode = <1>; 250 reg = <0x0b>; 251 label = "vdd_5p0"; 252 }; 253 254 channel@e { 255 gw,mode = <1>; 256 reg = <0xe>; 257 label = "vdd_arm"; 258 }; 259 260 channel@11 { 261 gw,mode = <1>; 262 reg = <0x11>; 263 label = "vdd_soc"; 264 }; 265 266 channel@14 { 267 gw,mode = <1>; 268 reg = <0x14>; 269 label = "vdd_3p0"; 270 }; 271 272 channel@17 { 273 gw,mode = <1>; 274 reg = <0x17>; 275 label = "vdd_1p5"; 276 }; 277 278 channel@1d { 279 gw,mode = <1>; 280 reg = <0x1d>; 281 label = "vdd_1p8"; 282 }; 283 284 channel@20 { 285 gw,mode = <1>; 286 reg = <0x20>; 287 label = "vdd_1p0"; 288 }; 289 290 channel@23 { 291 gw,mode = <1>; 292 reg = <0x23>; 293 label = "vdd_2p5"; 294 }; 295 296 channel@26 { 297 gw,mode = <1>; 298 reg = <0x26>; 299 label = "vdd_gps"; 300 }; 301 302 channel@29 { 303 gw,mode = <1>; 304 reg = <0x29>; 305 label = "vdd_an1"; 306 }; 307 }; 308 }; 309 310 gsc_gpio: gpio@23 { 311 compatible = "nxp,pca9555"; 312 reg = <0x23>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-parent = <&gsc>; 316 interrupts = <4>; 317 }; 318 319 eeprom1: eeprom@50 { 320 compatible = "atmel,24c02"; 321 reg = <0x50>; 322 pagesize = <16>; 323 }; 324 325 eeprom2: eeprom@51 { 326 compatible = "atmel,24c02"; 327 reg = <0x51>; 328 pagesize = <16>; 329 }; 330 331 eeprom3: eeprom@52 { 332 compatible = "atmel,24c02"; 333 reg = <0x52>; 334 pagesize = <16>; 335 }; 336 337 eeprom4: eeprom@53 { 338 compatible = "atmel,24c02"; 339 reg = <0x53>; 340 pagesize = <16>; 341 }; 342 343 rtc: ds1672@68 { 344 compatible = "dallas,ds1672"; 345 reg = <0x68>; 346 }; 347}; 348 349&i2c2 { 350 clock-frequency = <100000>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_i2c2>; 353 status = "okay"; 354 355 ltc3676: pmic@3c { 356 compatible = "lltc,ltc3676"; 357 reg = <0x3c>; 358 interrupt-parent = <&gpio1>; 359 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 360 361 regulators { 362 /* VDD_SOC (1+R1/R2 = 1.635) */ 363 reg_vdd_soc: sw1 { 364 regulator-name = "vddsoc"; 365 regulator-min-microvolt = <674400>; 366 regulator-max-microvolt = <1308000>; 367 lltc,fb-voltage-divider = <127000 200000>; 368 regulator-ramp-delay = <7000>; 369 regulator-boot-on; 370 regulator-always-on; 371 }; 372 373 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 374 reg_1p8v: sw2 { 375 regulator-name = "vdd1p8"; 376 regulator-min-microvolt = <1033310>; 377 regulator-max-microvolt = <2004000>; 378 lltc,fb-voltage-divider = <301000 200000>; 379 regulator-ramp-delay = <7000>; 380 regulator-boot-on; 381 regulator-always-on; 382 }; 383 384 /* VDD_ARM (1+R1/R2 = 1.635) */ 385 reg_vdd_arm: sw3 { 386 regulator-name = "vddarm"; 387 regulator-min-microvolt = <674400>; 388 regulator-max-microvolt = <1308000>; 389 lltc,fb-voltage-divider = <127000 200000>; 390 regulator-ramp-delay = <7000>; 391 regulator-boot-on; 392 regulator-always-on; 393 }; 394 395 /* VDD_DDR (1+R1/R2 = 2.105) */ 396 reg_vdd_ddr: sw4 { 397 regulator-name = "vddddr"; 398 regulator-min-microvolt = <868310>; 399 regulator-max-microvolt = <1684000>; 400 lltc,fb-voltage-divider = <221000 200000>; 401 regulator-ramp-delay = <7000>; 402 regulator-boot-on; 403 regulator-always-on; 404 }; 405 406 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 407 reg_2p5v: ldo2 { 408 regulator-name = "vdd2p5"; 409 regulator-min-microvolt = <2490375>; 410 regulator-max-microvolt = <2490375>; 411 lltc,fb-voltage-divider = <487000 200000>; 412 regulator-boot-on; 413 regulator-always-on; 414 }; 415 416 /* VDD_AUD_1P8: Audio codec */ 417 reg_aud_1p8v: ldo3 { 418 regulator-name = "vdd1p8a"; 419 regulator-min-microvolt = <1800000>; 420 regulator-max-microvolt = <1800000>; 421 regulator-boot-on; 422 }; 423 424 /* VDD_HIGH (1+R1/R2 = 4.17) */ 425 reg_3p0v: ldo4 { 426 regulator-name = "vdd3p0"; 427 regulator-min-microvolt = <3023250>; 428 regulator-max-microvolt = <3023250>; 429 lltc,fb-voltage-divider = <634000 200000>; 430 regulator-boot-on; 431 regulator-always-on; 432 }; 433 }; 434 }; 435}; 436 437&i2c3 { 438 clock-frequency = <100000>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_i2c3>; 441 status = "okay"; 442 443 codec: sgtl5000@a { 444 compatible = "fsl,sgtl5000"; 445 reg = <0x0a>; 446 clocks = <&clks IMX6QDL_CLK_CKO>; 447 VDDA-supply = <®_1p8v>; 448 VDDIO-supply = <®_3p3v>; 449 }; 450 451 touchscreen: egalax_ts@4 { 452 compatible = "eeti,egalax_ts"; 453 reg = <0x04>; 454 interrupt-parent = <&gpio1>; 455 interrupts = <11 2>; 456 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 457 }; 458 459 accel@1e { 460 compatible = "nxp,fxos8700"; 461 reg = <0x1e>; 462 }; 463}; 464 465&ldb { 466 status = "okay"; 467 468 lvds-channel@0 { 469 fsl,data-mapping = "spwg"; 470 fsl,data-width = <18>; 471 status = "okay"; 472 473 display-timings { 474 native-mode = <&timing0>; 475 timing0: hsd100pxn1 { 476 clock-frequency = <65000000>; 477 hactive = <1024>; 478 vactive = <768>; 479 hback-porch = <220>; 480 hfront-porch = <40>; 481 vback-porch = <21>; 482 vfront-porch = <7>; 483 hsync-len = <60>; 484 vsync-len = <10>; 485 }; 486 }; 487 }; 488}; 489 490&pcie { 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pinctrl_pcie>; 493 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 494 status = "okay"; 495}; 496 497&pwm2 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 500 status = "disabled"; 501}; 502 503&pwm3 { 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 506 status = "disabled"; 507}; 508 509&pwm4 { 510 #pwm-cells = <2>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_pwm4>; 513 status = "okay"; 514}; 515 516&ssi1 { 517 status = "okay"; 518}; 519 520&uart1 { 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_uart1>; 523 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 524 status = "okay"; 525}; 526 527&uart2 { 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pinctrl_uart2>; 530 status = "okay"; 531}; 532 533&uart5 { 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pinctrl_uart5>; 536 status = "okay"; 537}; 538 539&usbotg { 540 vbus-supply = <®_usb_otg_vbus>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pinctrl_usbotg>; 543 disable-over-current; 544 status = "okay"; 545}; 546 547&usbh1 { 548 vbus-supply = <®_usb_h1_vbus>; 549 status = "okay"; 550}; 551 552&usdhc3 { 553 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 554 pinctrl-0 = <&pinctrl_usdhc3>; 555 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 556 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 557 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 558 vmmc-supply = <®_3p3v>; 559 no-1-8-v; /* firmware will remove if board revision supports */ 560 status = "okay"; 561}; 562 563&wdog1 { 564 pinctrl-names = "default"; 565 pinctrl-0 = <&pinctrl_wdog>; 566 fsl,ext-reset-output; 567}; 568 569&iomuxc { 570 pinctrl_audmux: audmuxgrp { 571 fsl,pins = < 572 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 573 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 574 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 575 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 576 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 577 >; 578 }; 579 580 pinctrl_enet: enetgrp { 581 fsl,pins = < 582 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 583 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 584 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 585 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 586 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 587 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 588 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 589 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 590 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 591 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 592 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 593 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 594 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 595 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 596 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 597 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 598 >; 599 }; 600 601 pinctrl_flexcan1: flexcan1grp { 602 fsl,pins = < 603 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 604 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 605 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 606 >; 607 }; 608 609 pinctrl_gpio_leds: gpioledsgrp { 610 fsl,pins = < 611 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 612 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 613 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 614 >; 615 }; 616 617 pinctrl_gpmi_nand: gpminandgrp { 618 fsl,pins = < 619 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 620 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 621 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 622 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 623 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 624 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 625 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 626 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 627 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 628 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 629 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 630 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 631 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 632 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 633 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 634 >; 635 }; 636 637 pinctrl_i2c1: i2c1grp { 638 fsl,pins = < 639 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 640 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 641 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 642 >; 643 }; 644 645 pinctrl_i2c2: i2c2grp { 646 fsl,pins = < 647 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 648 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 649 >; 650 }; 651 652 pinctrl_i2c3: i2c3grp { 653 fsl,pins = < 654 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 655 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 656 >; 657 }; 658 659 pinctrl_pcie: pciegrp { 660 fsl,pins = < 661 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 662 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 663 >; 664 }; 665 666 pinctrl_pmic: pmicgrp { 667 fsl,pins = < 668 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 669 >; 670 }; 671 672 pinctrl_pps: ppsgrp { 673 fsl,pins = < 674 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 675 >; 676 }; 677 678 pinctrl_pwm2: pwm2grp { 679 fsl,pins = < 680 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 681 >; 682 }; 683 684 pinctrl_pwm3: pwm3grp { 685 fsl,pins = < 686 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 687 >; 688 }; 689 690 pinctrl_pwm4: pwm4grp { 691 fsl,pins = < 692 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 693 >; 694 }; 695 696 pinctrl_uart1: uart1grp { 697 fsl,pins = < 698 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 699 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 700 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 701 >; 702 }; 703 704 pinctrl_uart2: uart2grp { 705 fsl,pins = < 706 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 707 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 708 >; 709 }; 710 711 pinctrl_uart5: uart5grp { 712 fsl,pins = < 713 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 714 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 715 >; 716 }; 717 718 pinctrl_usbotg: usbotggrp { 719 fsl,pins = < 720 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 721 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 722 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 723 >; 724 }; 725 726 pinctrl_usdhc3: usdhc3grp { 727 fsl,pins = < 728 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 729 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 730 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 731 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 732 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 733 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 734 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 735 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 736 >; 737 }; 738 739 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 740 fsl,pins = < 741 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 742 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 743 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 744 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 745 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 746 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 747 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 748 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 749 >; 750 }; 751 752 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 753 fsl,pins = < 754 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 755 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 756 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 757 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 758 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 759 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 760 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 761 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 762 >; 763 }; 764 765 pinctrl_wdog: wdoggrp { 766 fsl,pins = < 767 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 768 >; 769 }; 770}; 771