1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6#include <dt-bindings/bus/ti-sysc.h> 7#include <dt-bindings/clock/omap4.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/omap.h> 11#include <dt-bindings/clock/omap4.h> 12 13/ { 14 compatible = "ti,omap4430", "ti,omap4"; 15 interrupt-parent = <&wakeupgen>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 chosen { }; 19 20 aliases { 21 i2c0 = &i2c1; 22 i2c1 = &i2c2; 23 i2c2 = &i2c3; 24 i2c3 = &i2c4; 25 mmc0 = &mmc1; 26 mmc1 = &mmc2; 27 mmc2 = &mmc3; 28 mmc3 = &mmc4; 29 mmc4 = &mmc5; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 rproc0 = &dsp; 35 rproc1 = &ipu; 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 cpu@0 { 43 compatible = "arm,cortex-a9"; 44 device_type = "cpu"; 45 next-level-cache = <&L2>; 46 reg = <0x0>; 47 48 clocks = <&dpll_mpu_ck>; 49 clock-names = "cpu"; 50 51 clock-latency = <300000>; /* From omap-cpufreq driver */ 52 }; 53 cpu@1 { 54 compatible = "arm,cortex-a9"; 55 device_type = "cpu"; 56 next-level-cache = <&L2>; 57 reg = <0x1>; 58 }; 59 }; 60 61 /* 62 * Note that 4430 needs cross trigger interface (CTI) supported 63 * before we can configure the interrupts. This means sampling 64 * events are not supported for pmu. Note that 4460 does not use 65 * CTI, see also 4460.dtsi. 66 */ 67 pmu { 68 compatible = "arm,cortex-a9-pmu"; 69 ti,hwmods = "debugss"; 70 }; 71 72 gic: interrupt-controller@48241000 { 73 compatible = "arm,cortex-a9-gic"; 74 interrupt-controller; 75 #interrupt-cells = <3>; 76 reg = <0x48241000 0x1000>, 77 <0x48240100 0x0100>; 78 interrupt-parent = <&gic>; 79 }; 80 81 L2: cache-controller@48242000 { 82 compatible = "arm,pl310-cache"; 83 reg = <0x48242000 0x1000>; 84 cache-unified; 85 cache-level = <2>; 86 }; 87 88 local-timer@48240600 { 89 compatible = "arm,cortex-a9-twd-timer"; 90 clocks = <&mpu_periphclk>; 91 reg = <0x48240600 0x20>; 92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; 93 interrupt-parent = <&gic>; 94 }; 95 96 wakeupgen: interrupt-controller@48281000 { 97 compatible = "ti,omap4-wugen-mpu"; 98 interrupt-controller; 99 #interrupt-cells = <3>; 100 reg = <0x48281000 0x1000>; 101 interrupt-parent = <&gic>; 102 }; 103 104 /* 105 * The soc node represents the soc top level view. It is used for IPs 106 * that are not memory mapped in the MPU view or for the MPU itself. 107 */ 108 soc { 109 compatible = "ti,omap-infra"; 110 mpu { 111 compatible = "ti,omap4-mpu"; 112 ti,hwmods = "mpu"; 113 sram = <&ocmcram>; 114 }; 115 116 iva { 117 compatible = "ti,ivahd"; 118 ti,hwmods = "iva"; 119 }; 120 }; 121 122 /* 123 * XXX: Use a flat representation of the OMAP4 interconnect. 124 * The real OMAP interconnect network is quite complex. 125 * Since it will not bring real advantage to represent that in DT for 126 * the moment, just use a fake OCP bus entry to represent the whole bus 127 * hierarchy. 128 */ 129 ocp { 130 compatible = "ti,omap4-l3-noc", "simple-bus"; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges; 134 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 135 reg = <0x44000000 0x1000>, 136 <0x44800000 0x2000>, 137 <0x45000000 0x1000>; 138 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 140 141 l4_wkup: interconnect@4a300000 { 142 }; 143 144 l4_cfg: interconnect@4a000000 { 145 }; 146 147 l4_per: interconnect@48000000 { 148 }; 149 150 l4_abe: interconnect@40100000 { 151 }; 152 153 ocmcram: sram@40304000 { 154 compatible = "mmio-sram"; 155 reg = <0x40304000 0xa000>; /* 40k */ 156 }; 157 158 gpmc: gpmc@50000000 { 159 compatible = "ti,omap4430-gpmc"; 160 reg = <0x50000000 0x1000>; 161 #address-cells = <2>; 162 #size-cells = <1>; 163 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 164 dmas = <&sdma 4>; 165 dma-names = "rxtx"; 166 gpmc,num-cs = <8>; 167 gpmc,num-waitpins = <4>; 168 ti,hwmods = "gpmc"; 169 ti,no-idle-on-init; 170 clocks = <&l3_div_ck>; 171 clock-names = "fck"; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 gpio-controller; 175 #gpio-cells = <2>; 176 }; 177 178 target-module@52000000 { 179 compatible = "ti,sysc-omap4", "ti,sysc"; 180 ti,hwmods = "iss"; 181 reg = <0x52000000 0x4>, 182 <0x52000010 0x4>; 183 reg-names = "rev", "sysc"; 184 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 185 ti,sysc-midle = <SYSC_IDLE_FORCE>, 186 <SYSC_IDLE_NO>, 187 <SYSC_IDLE_SMART>, 188 <SYSC_IDLE_SMART_WKUP>; 189 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 190 <SYSC_IDLE_NO>, 191 <SYSC_IDLE_SMART>, 192 <SYSC_IDLE_SMART_WKUP>; 193 ti,sysc-delay-us = <2>; 194 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; 195 clock-names = "fck"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0 0x52000000 0x1000000>; 199 200 /* No child device binding, driver in staging */ 201 }; 202 203 target-module@55082000 { 204 compatible = "ti,sysc-omap2", "ti,sysc"; 205 reg = <0x55082000 0x4>, 206 <0x55082010 0x4>, 207 <0x55082014 0x4>; 208 reg-names = "rev", "sysc", "syss"; 209 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 210 <SYSC_IDLE_NO>, 211 <SYSC_IDLE_SMART>; 212 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 213 SYSC_OMAP2_SOFTRESET | 214 SYSC_OMAP2_AUTOIDLE)>; 215 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; 216 clock-names = "fck"; 217 resets = <&prm_core 2>; 218 reset-names = "rstctrl"; 219 ranges = <0x0 0x55082000 0x100>; 220 #size-cells = <1>; 221 #address-cells = <1>; 222 223 mmu_ipu: mmu@0 { 224 compatible = "ti,omap4-iommu"; 225 reg = <0x0 0x100>; 226 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 227 #iommu-cells = <0>; 228 ti,iommu-bus-err-back; 229 }; 230 }; 231 232 target-module@4012c000 { 233 compatible = "ti,sysc-omap4", "ti,sysc"; 234 reg = <0x4012c000 0x4>, 235 <0x4012c010 0x4>; 236 reg-names = "rev", "sysc"; 237 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 238 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 239 <SYSC_IDLE_NO>, 240 <SYSC_IDLE_SMART>, 241 <SYSC_IDLE_SMART_WKUP>; 242 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; 243 clock-names = "fck"; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ 247 <0x4902c000 0x4902c000 0x1000>; /* L3 */ 248 249 /* No child device binding or driver in mainline */ 250 }; 251 252 dmm@4e000000 { 253 compatible = "ti,omap4-dmm"; 254 reg = <0x4e000000 0x800>; 255 interrupts = <0 113 0x4>; 256 ti,hwmods = "dmm"; 257 }; 258 259 emif1: emif@4c000000 { 260 compatible = "ti,emif-4d"; 261 reg = <0x4c000000 0x100>; 262 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 263 ti,hwmods = "emif1"; 264 ti,no-idle-on-init; 265 phy-type = <1>; 266 hw-caps-read-idle-ctrl; 267 hw-caps-ll-interface; 268 hw-caps-temp-alert; 269 }; 270 271 emif2: emif@4d000000 { 272 compatible = "ti,emif-4d"; 273 reg = <0x4d000000 0x100>; 274 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 275 ti,hwmods = "emif2"; 276 ti,no-idle-on-init; 277 phy-type = <1>; 278 hw-caps-read-idle-ctrl; 279 hw-caps-ll-interface; 280 hw-caps-temp-alert; 281 }; 282 283 dsp: dsp { 284 compatible = "ti,omap4-dsp"; 285 ti,bootreg = <&scm_conf 0x304 0>; 286 iommus = <&mmu_dsp>; 287 resets = <&prm_tesla 0>; 288 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; 289 firmware-name = "omap4-dsp-fw.xe64T"; 290 mboxes = <&mailbox &mbox_dsp>; 291 status = "disabled"; 292 }; 293 294 ipu: ipu@55020000 { 295 compatible = "ti,omap4-ipu"; 296 reg = <0x55020000 0x10000>; 297 reg-names = "l2ram"; 298 iommus = <&mmu_ipu>; 299 resets = <&prm_core 0>, <&prm_core 1>; 300 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; 301 firmware-name = "omap4-ipu-fw.xem3"; 302 mboxes = <&mailbox &mbox_ipu>; 303 status = "disabled"; 304 }; 305 306 aes1_target: target-module@4b501000 { 307 compatible = "ti,sysc-omap2", "ti,sysc"; 308 reg = <0x4b501080 0x4>, 309 <0x4b501084 0x4>, 310 <0x4b501088 0x4>; 311 reg-names = "rev", "sysc", "syss"; 312 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 313 SYSC_OMAP2_AUTOIDLE)>; 314 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 315 <SYSC_IDLE_NO>, 316 <SYSC_IDLE_SMART>, 317 <SYSC_IDLE_SMART_WKUP>; 318 ti,syss-mask = <1>; 319 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 320 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; 321 clock-names = "fck"; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 ranges = <0x0 0x4b501000 0x1000>; 325 326 aes1: aes@0 { 327 compatible = "ti,omap4-aes"; 328 reg = <0 0xa0>; 329 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 330 dmas = <&sdma 111>, <&sdma 110>; 331 dma-names = "tx", "rx"; 332 }; 333 }; 334 335 aes2_target: target-module@4b701000 { 336 compatible = "ti,sysc-omap2", "ti,sysc"; 337 reg = <0x4b701080 0x4>, 338 <0x4b701084 0x4>, 339 <0x4b701088 0x4>; 340 reg-names = "rev", "sysc", "syss"; 341 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 342 SYSC_OMAP2_AUTOIDLE)>; 343 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 344 <SYSC_IDLE_NO>, 345 <SYSC_IDLE_SMART>, 346 <SYSC_IDLE_SMART_WKUP>; 347 ti,syss-mask = <1>; 348 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 349 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; 350 clock-names = "fck"; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0x0 0x4b701000 0x1000>; 354 355 aes2: aes@0 { 356 compatible = "ti,omap4-aes"; 357 reg = <0 0xa0>; 358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 359 dmas = <&sdma 114>, <&sdma 113>; 360 dma-names = "tx", "rx"; 361 }; 362 }; 363 364 sham_target: target-module@4b100000 { 365 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 366 reg = <0x4b100100 0x4>, 367 <0x4b100110 0x4>, 368 <0x4b100114 0x4>; 369 reg-names = "rev", "sysc", "syss"; 370 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 371 SYSC_OMAP2_AUTOIDLE)>; 372 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 373 <SYSC_IDLE_NO>, 374 <SYSC_IDLE_SMART>; 375 ti,syss-mask = <1>; 376 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ 377 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>; 378 clock-names = "fck"; 379 #address-cells = <1>; 380 #size-cells = <1>; 381 ranges = <0x0 0x4b100000 0x1000>; 382 383 sham: sham@0 { 384 compatible = "ti,omap4-sham"; 385 reg = <0 0x300>; 386 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 387 dmas = <&sdma 119>; 388 dma-names = "rx"; 389 }; 390 }; 391 392 abb_mpu: regulator-abb-mpu { 393 compatible = "ti,abb-v2"; 394 regulator-name = "abb_mpu"; 395 #address-cells = <0>; 396 #size-cells = <0>; 397 ti,tranxdone-status-mask = <0x80>; 398 clocks = <&sys_clkin_ck>; 399 ti,settling-time = <50>; 400 ti,clock-cycles = <16>; 401 402 status = "disabled"; 403 }; 404 405 abb_iva: regulator-abb-iva { 406 compatible = "ti,abb-v2"; 407 regulator-name = "abb_iva"; 408 #address-cells = <0>; 409 #size-cells = <0>; 410 ti,tranxdone-status-mask = <0x80000000>; 411 clocks = <&sys_clkin_ck>; 412 ti,settling-time = <50>; 413 ti,clock-cycles = <16>; 414 415 status = "disabled"; 416 }; 417 418 sgx_module: target-module@56000000 { 419 compatible = "ti,sysc-omap4", "ti,sysc"; 420 reg = <0x5600fe00 0x4>, 421 <0x5600fe10 0x4>; 422 reg-names = "rev", "sysc"; 423 ti,sysc-midle = <SYSC_IDLE_FORCE>, 424 <SYSC_IDLE_NO>, 425 <SYSC_IDLE_SMART>, 426 <SYSC_IDLE_SMART_WKUP>; 427 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 428 <SYSC_IDLE_NO>, 429 <SYSC_IDLE_SMART>, 430 <SYSC_IDLE_SMART_WKUP>; 431 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; 432 clock-names = "fck"; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges = <0 0x56000000 0x2000000>; 436 437 /* 438 * Closed source PowerVR driver, no child device 439 * binding or driver in mainline 440 */ 441 }; 442 443 /* 444 * DSS is only using l3 mapping without l4 as noted in the TRM 445 * "10.1.3 DSS Register Manual" for omap4460. 446 */ 447 target-module@58000000 { 448 compatible = "ti,sysc-omap2", "ti,sysc"; 449 reg = <0x58000000 4>, 450 <0x58000014 4>; 451 reg-names = "rev", "syss"; 452 ti,syss-mask = <1>; 453 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, 454 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, 455 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, 456 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; 457 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges = <0 0x58000000 0x1000000>; 461 462 dss: dss@0 { 463 compatible = "ti,omap4-dss"; 464 reg = <0 0x80>; 465 status = "disabled"; 466 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; 467 clock-names = "fck"; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0 0 0x1000000>; 471 472 target-module@1000 { 473 compatible = "ti,sysc-omap2", "ti,sysc"; 474 reg = <0x1000 0x4>, 475 <0x1010 0x4>, 476 <0x1014 0x4>; 477 reg-names = "rev", "sysc", "syss"; 478 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 479 <SYSC_IDLE_NO>, 480 <SYSC_IDLE_SMART>; 481 ti,sysc-midle = <SYSC_IDLE_FORCE>, 482 <SYSC_IDLE_NO>, 483 <SYSC_IDLE_SMART>; 484 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 485 SYSC_OMAP2_ENAWAKEUP | 486 SYSC_OMAP2_SOFTRESET | 487 SYSC_OMAP2_AUTOIDLE)>; 488 ti,syss-mask = <1>; 489 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 490 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 491 clock-names = "fck", "sys_clk"; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 ranges = <0 0x1000 0x1000>; 495 496 dispc@0 { 497 compatible = "ti,omap4-dispc"; 498 reg = <0 0x1000>; 499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; 501 clock-names = "fck"; 502 }; 503 }; 504 505 target-module@2000 { 506 compatible = "ti,sysc-omap2", "ti,sysc"; 507 reg = <0x2000 0x4>, 508 <0x2010 0x4>, 509 <0x2014 0x4>; 510 reg-names = "rev", "sysc", "syss"; 511 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 512 <SYSC_IDLE_NO>, 513 <SYSC_IDLE_SMART>; 514 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 515 SYSC_OMAP2_AUTOIDLE)>; 516 ti,syss-mask = <1>; 517 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 518 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 519 clock-names = "fck", "sys_clk"; 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges = <0 0x2000 0x1000>; 523 524 rfbi: encoder@0 { 525 reg = <0 0x1000>; 526 status = "disabled"; 527 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; 528 clock-names = "fck", "ick"; 529 }; 530 }; 531 532 target-module@3000 { 533 compatible = "ti,sysc-omap2", "ti,sysc"; 534 reg = <0x3000 0x4>; 535 reg-names = "rev"; 536 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 537 clock-names = "sys_clk"; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges = <0 0x3000 0x1000>; 541 542 venc: encoder@0 { 543 compatible = "ti,omap4-venc"; 544 reg = <0 0x1000>; 545 status = "disabled"; 546 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; 547 clock-names = "fck"; 548 }; 549 }; 550 551 target-module@4000 { 552 compatible = "ti,sysc-omap2", "ti,sysc"; 553 reg = <0x4000 0x4>, 554 <0x4010 0x4>, 555 <0x4014 0x4>; 556 reg-names = "rev", "sysc", "syss"; 557 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 558 <SYSC_IDLE_NO>, 559 <SYSC_IDLE_SMART>; 560 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 561 SYSC_OMAP2_ENAWAKEUP | 562 SYSC_OMAP2_SOFTRESET | 563 SYSC_OMAP2_AUTOIDLE)>; 564 ti,syss-mask = <1>; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 ranges = <0 0x4000 0x1000>; 568 569 dsi1: encoder@0 { 570 compatible = "ti,omap4-dsi"; 571 reg = <0 0x200>, 572 <0x200 0x40>, 573 <0x300 0x20>; 574 reg-names = "proto", "phy", "pll"; 575 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 576 status = "disabled"; 577 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 578 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 579 clock-names = "fck", "sys_clk"; 580 581 #address-cells = <1>; 582 #size-cells = <0>; 583 }; 584 }; 585 586 target-module@5000 { 587 compatible = "ti,sysc-omap2", "ti,sysc"; 588 reg = <0x5000 0x4>, 589 <0x5010 0x4>, 590 <0x5014 0x4>; 591 reg-names = "rev", "sysc", "syss"; 592 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 593 <SYSC_IDLE_NO>, 594 <SYSC_IDLE_SMART>; 595 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 596 SYSC_OMAP2_ENAWAKEUP | 597 SYSC_OMAP2_SOFTRESET | 598 SYSC_OMAP2_AUTOIDLE)>; 599 ti,syss-mask = <1>; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 ranges = <0 0x5000 0x1000>; 603 604 dsi2: encoder@0 { 605 compatible = "ti,omap4-dsi"; 606 reg = <0 0x200>, 607 <0x200 0x40>, 608 <0x300 0x20>; 609 reg-names = "proto", "phy", "pll"; 610 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 611 status = "disabled"; 612 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, 613 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 614 clock-names = "fck", "sys_clk"; 615 616 #address-cells = <1>; 617 #size-cells = <0>; 618 }; 619 }; 620 621 target-module@6000 { 622 compatible = "ti,sysc-omap4", "ti,sysc"; 623 reg = <0x6000 0x4>, 624 <0x6010 0x4>; 625 reg-names = "rev", "sysc"; 626 /* 627 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP 628 * but HDMI audio will fail with them. 629 */ 630 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 631 <SYSC_IDLE_NO>; 632 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 633 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, 634 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; 635 clock-names = "fck", "dss_clk"; 636 #address-cells = <1>; 637 #size-cells = <1>; 638 ranges = <0 0x6000 0x2000>; 639 640 hdmi: encoder@0 { 641 compatible = "ti,omap4-hdmi"; 642 reg = <0 0x200>, 643 <0x200 0x100>, 644 <0x300 0x100>, 645 <0x400 0x1000>; 646 reg-names = "wp", "pll", "phy", "core"; 647 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 648 status = "disabled"; 649 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, 650 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; 651 clock-names = "fck", "sys_clk"; 652 dmas = <&sdma 76>; 653 dma-names = "audio_tx"; 654 }; 655 }; 656 }; 657 }; 658 }; 659}; 660 661#include "omap4-l4.dtsi" 662#include "omap4-l4-abe.dtsi" 663#include "omap44xx-clocks.dtsi" 664 665&prm { 666 prm_tesla: prm@400 { 667 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; 668 reg = <0x400 0x100>; 669 #reset-cells = <1>; 670 }; 671 672 prm_abe: prm@500 { 673 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; 674 reg = <0x500 0x100>; 675 #power-domain-cells = <0>; 676 }; 677 678 prm_core: prm@700 { 679 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; 680 reg = <0x700 0x100>; 681 #reset-cells = <1>; 682 }; 683 684 prm_ivahd: prm@f00 { 685 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; 686 reg = <0xf00 0x100>; 687 #reset-cells = <1>; 688 }; 689 690 prm_device: prm@1b00 { 691 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; 692 reg = <0x1b00 0x40>; 693 #reset-cells = <1>; 694 }; 695}; 696 697/* Preferred always-on timer for clockevent */ 698&timer1_target { 699 ti,no-reset-on-init; 700 ti,no-idle; 701 timer@0 { 702 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; 703 assigned-clock-parents = <&sys_32k_ck>; 704 }; 705}; 706