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/arch/c6x/lib/
Dcsum_64plus.S32 AND .S1 3,A4,A1
34 OR .L2X B0,A1,B0 ; non aligned condition
37 || MV .D1X B5,A1 ; words condition
38 [!A1] B .S1 L8
55 ZERO .D1 A1
59 [!A1] BNOP .S1 L8,5
295 || ZERO .D1 A1
299 || [A0] LDBU .D1T1 *A4++,A1
304 || SHL .S1 A0,8,A1
316 || ADD .L1 A0,A1,A1
[all …]
Ddivi.S10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
29 || cmpgt .l1 0, A4, A1
32 [A1] neg .l1 A4, A4
34 || xor .s1x A1, B1, A1
35 [A1] addkpc .s2 _divu_ret, B3, 4
Dllshru.S12 mv .l1x B4,A1
13 [!A1] b .s2 B3 ; return if zero shift count
15 sub .d1 A0,A1,A0
20 || [A2] shru .s1 A4,A1,A4
24 [A2] shru .s1 A5,A1,A5
Dllshl.S12 mv .l1x B4,A1
13 [!A1] b .s2 B3 ; just return if zero shift
15 sub .d1 A0,A1,A0
19 || [A2] shl .s1 A5,A1,A5
23 [A2] shl .s1 A4,A1,A4
Dllshr.S12 mv .l1x B4,A1
13 [!A1] b .s2 B3 ; return if zero shift count
15 sub .d1 A0,A1,A0
20 || [A2] shru .s1 A4,A1,A4
24 [A2] shr .s1 A5,A1,A5
Dremi.S10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
29 || cmpgt .l1 0, A4, A1
34 [A1] neg .l1 A4, A4
36 || xor .s2x B2, A1, B0
Dmemcpy_64plus.S14 || AND .S1 0x2,A6,A1
20 [A1] LDB .D2T1 *B4++,A7
21 [A1] LDB .D2T1 *B4++,A8
28 [A1] STB .D1T1 A7,*A3++
29 [A1] STB .D1T1 A8,*A3++
Dremu.S10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
39 cmpltu .l1x A4, B4, A1
40 [!A1] sub .l1x A4, B4, A4
Ddivremi.S11 || cmpgt .l1 0, A4, A1
16 [A1] neg .l1 A4, A4
18 || xor .s2x B2, A1, B0
Ddivu.S10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
78 || mvk .s1 32, A1
79 sub .l1 A1, A6, A6
Dstrasgi.S15 ldw .d2t1 *B4++, A1
29 || mv .s2x A1, B5
36 [B0] ldw .d2t1 *B4++, A1
66 [B0] stw .d1t1 A1, *A4++
Dmpyll.S28 mpy32u .m1x A4,B4,A1:A0 ; X0*Y0
36 add .s1 A1,A5,A5
Ddivremu.S66 || mvk .s1 32, A1
67 sub .l1 A1, A6, A6
/arch/arm/boot/dts/
Darmada-388-clearfog-pro.dts3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
10 model = "SolidRun Clearfog Pro A1";
Darmada-388-clearfog-base.dts3 * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
12 model = "SolidRun Clearfog Base A1";
Darmada-388-clearfog.dts3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
12 model = "SolidRun Clearfog A1";
/arch/mips/mm/
Dpage.c42 #define A1 5 macro
371 uasm_i_ld(buf, reg, off, A1); in build_copy_load()
373 uasm_i_lw(buf, reg, off, A1); in build_copy_load()
392 _uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1); in build_copy_load_pref()
495 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
540 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
578 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
/arch/m68k/fpsp040/
Dsatan.S317 |--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U
319 |--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3))
320 |--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3.
322 |--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED
332 fmuld ATANA1,%fp1 | ...A1*U*V
333 fmulx %fp2,%fp1 | ...A1*U*V*(A2+V*(A3+V))
Dsetox.S128 | p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))
130 | made as "short" as possible: A1 (which is 1/2), A4 and A5
138 | [ S*(A1 + S*(A3 + S*A5)) ]
513 |-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))
515 |--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))]
538 fadds #0x3F000000,%fp2 | ...fp2 IS A1+S*(A3+S*A5)
541 fmulx %fp1,%fp2 | ...fp2 IS S*(A1+S*(A3+S*A5))
680 |-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*(A5 + R*A6)))))
682 |--[R*S*(A2+S*(A4+S*A6))] + [R+S*(A1+S*(A3+S*A5))]
707 fadds #0x3F000000,%fp3 | ...fp3 IS A1+S*(A3+S*A5)
[all …]
Dslogn.S388 |--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS
389 |--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
404 faddd LOGA1,%fp2 | ...A1+V*(A3+V*A5)
408 fmulx %fp3,%fp2 | ...V*(A1+V*(A3+V*A5)), FP3 RELEASED
411 faddx %fp2,%fp0 | ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED
/arch/arm64/boot/dts/amlogic/
Dmeson-sm1-khadas-vim3l-android.dts87 sensorhub,irq1-gpio = <&gpio GPIOA_1 0>; /* A1 -> PB5 */
89 interrupts = <62 IRQ_TYPE_EDGE_RISING>; /* A1 */
112 sensorhub,wakeup-gpio = <&gpio GPIOA_1 0>; /* A1 -> PA0 */
Dmeson-a1-ad401.dts12 model = "Amlogic Meson A1 AD401 Development Board";
/arch/c6x/kernel/
Dswitch_to.S50 || LDDW .D1T1 *+A5(THREAD_RICL_ICL),A1:A0
68 || MV .L2X A1,B1
Dentry.S91 || STDW .D1T1 A1:A0,*A15--[1]
148 LDDW .D1T1 *++A15[1],A1:A0
255 MVKL .S1 schedule,A1
256 MVKH .S1 schedule,A1
257 B .S2X A1
310 MVK .S1 _TIF_WORK_MASK,A1
313 AND .D1 A1,A2,A0
/arch/h8300/lib/
Dudivsi3.S13 divxu.w A1,A2P
15 divxu.w A1,A0P

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