| /arch/c6x/lib/ |
| D | strasgi.S | 24 || cmpltu .l2 B2, B7, B0
28 || [B0] ldw .d2t1 *B4++, A0
32 [B0] sub .d2 B6, 24, B7
33 || [B0] b .s2 _strasgi_loop
34 || cmpltu .l2 B1, B6, B0
36 [B0] ldw .d2t1 *B4++, A1
39 || cmpltu .l2 12, B6, B0
41 [B0] ldw .d2t1 *B4++, A5
44 || cmpltu .l2 8, B6, B0
46 [B0] ldw .d2t1 *B4++, A7
[all …]
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| D | csum_64plus.S | 33 || AND .S2 3,B4,B0
34 OR .L2X B0,A1,B0 ; non aligned condition
39 [B0] BNOP .S1 L6,5
79 CMPGT .L2 B5,0,B0
80 [!B0] BNOP .S1 L82,4
112 L82: AND .S2X 1,A6,B0
113 [!B0] BNOP .S1 L9,5
136 L9: SHRU .S2X A9,16,B0
137 [!B0] BNOP .S1 L10,5
187 SHL .S2 B4,2,B0
[all …]
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| D | remi.S | 10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
36 || xor .s2x B2, A1, B0
39 [B0] addkpc .s2 _divu_ret_1, B3, 1
40 [!B0] addkpc .s2 _divu_ret_2, B3, 1
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| D | remu.S | 10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
44 cmpgt .l2 B1, 7, B0
50 || [B0] b .s1 _remu_loop
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| D | divremi.S | 18 || xor .s2x B2, A1, B0
21 [B0] addkpc .s2 _divu_ret_1, B3, 1
22 [!B0] addkpc .s2 _divu_ret_2, B3, 1
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| D | divi.S | 10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
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| D | memcpy_64plus.S | 15 || AND .L2X 0x4,A6,B0
22 [B0] LDNW .D2T1 *B4++,A9
30 [B0] STNW .D1T1 A9,*A3++ ; return when len < 8
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| D | divu.S | 10 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
11 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
12 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
59 cmpgt .l2 B1, 7, B0
64 || [B0] b .s1 _divu_loop
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| D | mpyll.S | 30 || mpy32u .m2x B5,A4,B1:B0 ; X0*Y1 (don't need upper 32-bits)
35 add .l1x A2,B0,A5
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| D | divremu.S | 47 cmpgt .l2 B1, 7, B0
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| /arch/c6x/kernel/ |
| D | entry.S | 48 STW .D2T2 B0,*SP--[2] ; save original B0
49 MVKL .S2 current_ksp,B0
50 MVKH .S2 current_ksp,B0
51 LDW .D2T2 *B0,B1 ; KSP
55 XOR .D2 SP,B1,B0 ; (SP ^ KSP)
56 LDW .D2T2 *+SP[1],B1 ; restore B0/B1
57 LDW .D2T2 *++SP[2],B0
58 SHR .S2 B0,THREAD_SHIFT,B0 ; 0 if already using kstack
59 [B0] STDW .D2T2 SP:DP,*--B1[1] ; user: save user sp/dp kstack
60 [B0] MV .S2 B1,SP ; and switch to kstack
[all …]
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| D | head.S | 24 MVKL .S2 current_ksp,B0
25 MVKH .S2 current_ksp,B0
26 LDW .D2T2 *B0,B15
29 SHR .S2 B6,3,B0 ; number of dwords to clear
33 BDEC .S2 bss_loop,B0
35 CMPLT .L2 B0,0,B1
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| D | switch_to.S | 25 || MVC .S2 ILC,B0
31 || STDW .D2T2 B1:B0,*+B5(THREAD_RICL_ICL)
64 MV .L2X A0,B0
67 MVC .S2 B0,ILC
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| /arch/arm64/boot/dts/amd/ |
| D | amd-overdrive-rev-b0.dts | 4 * Note: For Seattle Rev.B0
14 model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
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| D | husky.dts | 4 * Note: Based-on AMD Seattle Rev.B0
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| /arch/xtensa/include/uapi/asm/ |
| D | termbits.h | 131 #define B0 0000000 /* hang up */ macro
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| /arch/powerpc/include/uapi/asm/ |
| D | termbits.h | 122 #define B0 0000000 /* hang up */ macro
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| /arch/parisc/include/uapi/asm/ |
| D | termbits.h | 115 #define B0 0000000 /* hang up */ macro
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| /arch/ia64/include/uapi/asm/ |
| D | termbits.h | 123 #define B0 0000000 /* hang up */ macro
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| /arch/mips/include/uapi/asm/ |
| D | termbits.h | 138 #define B0 0000000 /* hang up */ macro
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| /arch/alpha/include/uapi/asm/ |
| D | termbits.h | 134 #define B0 0000000 /* hang up */ macro
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| /arch/sparc/include/uapi/asm/ |
| D | termbits.h | 146 #define B0 0x00000000 /* hang up */ macro
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| /arch/mips/boot/dts/pic32/ |
| D | pic32mzda_sk.dts | 127 pins = "B0";
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| /arch/ia64/kernel/ |
| D | entry.h | 57 .spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off); \
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| D | entry.S | 277 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
297 st8 [r14]=r21,SW(B1)-SW(B0) // save b0
371 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
742 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
746 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
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