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Searched refs:Buffer (Results 1 – 8 of 8) sorted by relevance

/arch/mips/fw/arc/
Dfile.c16 ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) in ArcRead() argument
18 return ARC_CALL4(read, FileID, Buffer, N, Count); in ArcRead()
22 ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) in ArcWrite() argument
24 return ARC_CALL4(write, FileID, Buffer, N, Count); in ArcWrite()
/arch/arm/mm/
Dproc-xscale.S216 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
245 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
269 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
291 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
312 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
336 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
353 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
371 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
474 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
562 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
DKconfig36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
166 Branch Target Buffer, Unified TLB and cache line size 16.
1045 bool "PL310 errata: no automatic Store Buffer drain"
1047 On revisions of the PL310 prior to r3p2, the Store Buffer does
/arch/arm/boot/dts/
Daspeed-bmc-opp-mihawk.dts523 * CLK Buffer 9FGS9092
524 * CLK Buffer 9DBL0651BKILFT
525 * CLK Buffer 9DBL0651BKILFT
Daspeed-bmc-opp-mowgli.dts430 * CLK Buffer 9FGS9092
Dtegra20-colibri.dtsi61 * Buffer Enables for nPWE and RDnWR (On-module,
/arch/arm/
DKconfig952 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
958 optimisation in the Cortex-A9 Store Buffer may lead to data
960 register of the Cortex-A9 which disables the Store Buffer
988 bool "ARM errata: no automatic Store Buffer drain"
992 r2p0) erratum. The Store Buffer does not have any automatic draining
/arch/mips/
DKconfig1406 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),