| /arch/powerpc/perf/ |
| D | generic-compat-pmu.c | 97 #define C(x) PERF_COUNT_HW_CACHE_##x macro
104 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
105 [ C(L1D) ] = {
106 [ C(OP_READ) ] = {
107 [ C(RESULT_ACCESS) ] = 0,
108 [ C(RESULT_MISS) ] = 0,
110 [ C(OP_WRITE) ] = {
111 [ C(RESULT_ACCESS) ] = 0,
112 [ C(RESULT_MISS) ] = 0,
114 [ C(OP_PREFETCH) ] = {
[all …]
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| D | e6500-pmu.c | 28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
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| D | power8-pmu.c | 249 #define C(x) PERF_COUNT_HW_CACHE_##x macro
256 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
257 [ C(L1D) ] = {
258 [ C(OP_READ) ] = {
259 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
260 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
262 [ C(OP_WRITE) ] = {
263 [ C(RESULT_ACCESS) ] = 0,
264 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
266 [ C(OP_PREFETCH) ] = {
[all …]
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| D | e500-pmu.c | 27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
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| D | power10-pmu.c | 272 #define C(x) PERF_COUNT_HW_CACHE_##x macro
279 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
280 [C(L1D)] = {
281 [C(OP_READ)] = {
282 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
283 [C(RESULT_MISS)] = PM_LD_MISS_L1,
285 [C(OP_WRITE)] = {
286 [C(RESULT_ACCESS)] = 0,
287 [C(RESULT_MISS)] = PM_ST_MISS_L1,
289 [C(OP_PREFETCH)] = {
[all …]
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| D | power9-pmu.c | 308 #define C(x) PERF_COUNT_HW_CACHE_##x macro
315 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
316 [ C(L1D) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
319 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = 0,
323 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
325 [ C(OP_PREFETCH) ] = {
[all …]
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| D | mpc7450-pmu.c | 357 #define C(x) PERF_COUNT_HW_CACHE_##x macro
364 static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
365 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
366 [C(OP_READ)] = { 0, 0x225 },
367 [C(OP_WRITE)] = { 0, 0x227 },
368 [C(OP_PREFETCH)] = { 0, 0 },
370 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
371 [C(OP_READ)] = { 0x129, 0x115 },
372 [C(OP_WRITE)] = { -1, -1 },
373 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
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| D | ppc970-pmu.c | 430 #define C(x) PERF_COUNT_HW_CACHE_##x macro
437 static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
438 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
439 [C(OP_READ)] = { 0x8810, 0x3810 },
440 [C(OP_WRITE)] = { 0x7810, 0x813 },
441 [C(OP_PREFETCH)] = { 0x731, 0 },
443 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
444 [C(OP_READ)] = { 0, 0 },
445 [C(OP_WRITE)] = { -1, -1 },
446 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
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| D | power7-pmu.c | 331 #define C(x) PERF_COUNT_HW_CACHE_##x macro
338 static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
339 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
340 [C(OP_READ)] = { 0xc880, 0x400f0 },
341 [C(OP_WRITE)] = { 0, 0x300f0 },
342 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
344 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
345 [C(OP_READ)] = { 0, 0x200fc },
346 [C(OP_WRITE)] = { -1, -1 },
347 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
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| /arch/arc/include/asm/ |
| D | perf_event.h | 123 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
126 static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127 [C(L1D)] = {
128 [C(OP_READ)] = {
129 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
130 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
132 [C(OP_WRITE)] = {
133 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
134 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
136 [C(OP_PREFETCH)] = {
[all …]
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| /arch/sh/kernel/cpu/sh4a/ |
| D | perf_event.c | 109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
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| /arch/sh/kernel/cpu/sh4/ |
| D | perf_event.c | 84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
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| /arch/x86/events/zhaoxin/ |
| D | core.c | 51 [C(L1D)] = {
52 [C(OP_READ)] = {
53 [C(RESULT_ACCESS)] = 0x0042,
54 [C(RESULT_MISS)] = 0x0538,
56 [C(OP_WRITE)] = {
57 [C(RESULT_ACCESS)] = 0x0043,
58 [C(RESULT_MISS)] = 0x0562,
60 [C(OP_PREFETCH)] = {
61 [C(RESULT_ACCESS)] = -1,
62 [C(RESULT_MISS)] = -1,
[all …]
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| /arch/x86/events/intel/ |
| D | p6.c | 28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
30 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
31 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
33 [ C(OP_WRITE) ] = {
34 [ C(RESULT_ACCESS) ] = 0,
35 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
37 [ C(OP_PREFETCH) ] = {
38 [ C(RESULT_ACCESS) ] = 0,
39 [ C(RESULT_MISS) ] = 0,
[all …]
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| D | knc.c | 26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
32 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
34 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
38 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
42 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
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| D | core.c | 437 [ C(L1D ) ] = {
438 [ C(OP_READ) ] = {
439 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
440 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
442 [ C(OP_WRITE) ] = {
443 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
444 [ C(RESULT_MISS) ] = 0x0,
446 [ C(OP_PREFETCH) ] = {
447 [ C(RESULT_ACCESS) ] = 0x0,
448 [ C(RESULT_MISS) ] = 0x0,
[all …]
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| /arch/arm/kernel/ |
| D | perf_event_v7.c | 179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
184 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
185 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
187 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
189 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
190 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
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| D | perf_event_v6.c | 96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
101 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
109 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
110 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
112 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
113 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
[all …]
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| /arch/x86/events/amd/ |
| D | core.c | 26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
28 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
29 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
31 [ C(OP_WRITE) ] = {
32 [ C(RESULT_ACCESS) ] = 0,
33 [ C(RESULT_MISS) ] = 0,
35 [ C(OP_PREFETCH) ] = {
36 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
37 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
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| /arch/nds32/include/asm/ |
| D | pmu.h | 14 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
244 [C(L1D)] = {
245 [C(OP_READ)] = {
246 [C(RESULT_ACCESS)] =
248 [C(RESULT_MISS)] =
251 [C(OP_WRITE)] = {
252 [C(RESULT_ACCESS)] =
254 [C(RESULT_MISS)] =
257 [C(OP_PREFETCH)] = {
258 [C(RESULT_ACCESS)] =
[all …]
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| /arch/sparc/kernel/ |
| D | perf_event.c | 147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
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| /arch/riscv/kernel/ |
| D | perf_event.c | 52 #define C(x) PERF_COUNT_HW_CACHE_##x macro
56 [C(L1D)] = {
57 [C(OP_READ)] = {
58 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
59 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
61 [C(OP_WRITE)] = {
62 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
63 [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
65 [C(OP_PREFETCH)] = {
66 [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
[all …]
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| /arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
1019 [C(L1D)] = {
1026 [C(OP_READ)] = {
1027 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1028 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1030 [C(OP_WRITE)] = {
1031 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1035 [C(L1I)] = {
1036 [C(OP_READ)] = {
[all …]
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| /arch/arm64/kernel/ |
| D | perf_event.c | 60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
[all …]
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| /arch/csky/kernel/ |
| D | perf_event.c | 727 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
729 static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
730 [C(L1D)] = {
732 [C(OP_READ)] = {
733 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
734 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
736 [C(OP_WRITE)] = {
737 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
738 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
740 [C(OP_PREFETCH)] = {
[all …]
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