| /arch/sparc/include/asm/ |
| D | visasm.h | 17 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
23 297: wr %g0, FPRS_FEF, %fprs; \
39 andcc %o5, FPRS_FEF, %g0; \
43 297: wr %o5, FPRS_FEF, %fprs;
60 " " : : "i" (FPRS_FEF|FPRS_DU) : in save_and_clear_fpu()
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| /arch/sparc/kernel/ |
| D | rtrap_64.S | 59 andcc %l5, FPRS_FEF, %g0
335 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
338 andcc %l2, FPRS_FEF, %g0
343 wr %g1, FPRS_FEF, %fprs
367 5: wr %g0, FPRS_FEF, %fprs
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| D | fpu_traps.S | 12 andcc %g5, FPRS_FEF, %g0
25 wr %g0, FPRS_FEF, %fprs
26 andcc %g5, FPRS_FEF, %g0
192 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
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| D | unaligned_64.c | 553 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_ldf_stq()
554 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_ldf_stq()
635 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_lddfmna()
636 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_lddfmna()
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| D | ptrace_64.c | 363 if (fprs & FPRS_FEF) { in fpregs64_get()
406 fprs |= (FPRS_FEF | FPRS_DL | FPRS_DU); in fpregs64_set()
688 enabled = t->fpsaved[0] & FPRS_FEF; in fpregs32_get()
737 fprs |= (FPRS_FEF | FPRS_DL); in fpregs32_set()
841 if (t->fpsaved[0] & FPRS_FEF) in getfpregs_get()
881 fprs |= (FPRS_FEF | FPRS_DL); in setfpregs_set()
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| D | signal32.c | 368 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
396 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
502 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
530 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
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| D | signal_64.c | 158 fenab = (current_thread_info()->fpsaved[0] & FPRS_FEF); in sparc64_get_context()
364 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame()
385 if (current_thread_info()->fpsaved[0] & FPRS_FEF) { in setup_rt_frame()
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| D | prom_irqtrans.c | 366 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| /arch/sparc/lib/ |
| D | NG4memcpy.S | 14 #define FPRS_FEF 0x04 macro
21 andcc %o5, FPRS_FEF, %g0; \
23 wr %g0, FPRS_FEF, %fprs; \
29 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
32 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | xor.S | 29 andcc %o5, FPRS_FEF|FPRS_DU, %g0
34 0: wr %g0, FPRS_FEF, %fprs
99 andcc %o5, FPRS_FEF|FPRS_DU, %g0
104 0: wr %g0, FPRS_FEF, %fprs
166 andcc %o5, FPRS_FEF|FPRS_DU, %g0
171 0: wr %g0, FPRS_FEF, %fprs
253 andcc %o5, FPRS_FEF|FPRS_DU, %g0
258 0: wr %g0, FPRS_FEF, %fprs
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| D | U3memcpy.S | 14 #define FPRS_FEF 0x04 macro
16 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
18 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
20 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
21 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | VISsave.S | 48 mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5
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| D | NG2memcpy.S | 16 #define FPRS_FEF 0x04 macro
18 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
20 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
22 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
23 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | U1memcpy.S | 17 #define FPRS_FEF 0x04 macro
19 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
21 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
23 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
24 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| /arch/sparc/include/uapi/asm/ |
| D | pstate.h | 85 #define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */ macro
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| /arch/sparc/math-emu/ |
| D | math_64.c | 418 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in do_mathemu()
419 current_thread_info()->fpsaved[0] = FPRS_FEF; in do_mathemu()
|