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Searched refs:MMCR1_TTM0SEL_SH (Results 1 – 5 of 5) sorted by relevance

/arch/powerpc/perf/
Dpower7-pmu.c33 #define MMCR1_TTM0SEL_SH 60 macro
290 << (MMCR1_TTM0SEL_SH - 4 * pmc); in power7_compute_mmcr()
Dpower6-pmu.c37 #define MMCR1_TTM0SEL_SH 60 macro
38 #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
Dpower5-pmu.c45 #define MMCR1_TTM0SEL_SH 62 macro
459 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; in power5_compute_mmcr()
Dpower5+-pmu.c45 #define MMCR1_TTM0SEL_SH 62 macro
519 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; in power5p_compute_mmcr()
Dppc970-pmu.c50 #define MMCR1_TTM0SEL_SH 62 macro