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Searched refs:MSR_P4_TBPU_ESCR0 (Results 1 – 3 of 3) sorted by relevance

/arch/x86/oprofile/
Dop_model_p4.c333 { { CTR_MS_0, MSR_P4_TBPU_ESCR0},
339 { { CTR_MS_0, MSR_P4_TBPU_ESCR0},
/arch/x86/events/intel/
Dp4.c347 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
357 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
1171 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
/arch/x86/include/asm/
Dmsr-index.h922 #define MSR_P4_TBPU_ESCR0 0x000003c2 macro