Searched refs:NR_IRQS_LEGACY (Results 1 – 17 of 17) sorted by relevance
59 #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)60 #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)61 #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)62 #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)63 #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)64 #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)65 #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)66 #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)67 #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)68 #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)[all …]
143 #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)144 #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)145 #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)146 #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)147 #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)148 #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)149 #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)150 #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)151 #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)152 #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)[all …]
24 #define INT_CAMERA (NR_IRQS_LEGACY + 1)25 #define INT_FIQ (NR_IRQS_LEGACY + 3)26 #define INT_RTDX (NR_IRQS_LEGACY + 6)27 #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7)28 #define INT_HOST (NR_IRQS_LEGACY + 8)29 #define INT_ABORT (NR_IRQS_LEGACY + 9)30 #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13)31 #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14)32 #define INT_UART3 (NR_IRQS_LEGACY + 15)33 #define INT_TIMER3 (NR_IRQS_LEGACY + 16)[all …]
6 #define NR_IRQS_LEGACY 16 macro9 #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)11 #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
5 #define NR_IRQS_LEGACY 16 macro10 #define NR_IRQS NR_IRQS_LEGACY41 return NR_IRQS_LEGACY; in nr_legacy_irqs()
128 #define NR_IRQS_LEGACY 16 macro143 #define NR_IRQS NR_IRQS_LEGACY
146 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))206 #define gsi_top (NR_IRQS_LEGACY)
27 #define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS macro
157 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; in ams_delta_init_fiq()197 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; in ams_delta_init_fiq()
236 omap_l2_irq -= NR_IRQS_LEGACY; in omap1_init_irq()
106 cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
12 #define NR_IRQS_LEGACY NR_IRQS_BASE macro
15 #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x))
430 .nr_legacy_irqs = NR_IRQS_LEGACY,
98 static u32 isa_irq_to_gsi[NR_IRQS_LEGACY] __read_mostly = {349 if (bus_irq >= NR_IRQS_LEGACY) { in mp_override_legacy_irq()482 if (bus_irq < NR_IRQS_LEGACY) in acpi_sci_ioapic_setup()
578 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { in pci_xen_initial_domain()
665 if (gsi_top <= NR_IRQS_LEGACY) in arch_probe_nr_irqs()