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Searched refs:PMCR (Results 1 – 10 of 10) sorted by relevance

/arch/sh/kernel/cpu/sh4/
Dperf_event.c17 #define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) macro
212 tmp = __raw_readw(PMCR(idx)); in sh7750_pmu_disable()
214 __raw_writew(tmp, PMCR(idx)); in sh7750_pmu_disable()
219 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); in sh7750_pmu_enable()
220 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); in sh7750_pmu_enable()
228 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); in sh7750_pmu_disable_all()
236 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i)); in sh7750_pmu_enable_all()
/arch/arm/mach-sa1100/
Dsleep.S110 ldr r12, =PMCR
139 @ Step 6 set force sleep bit in PMCR
Dsimpad.c249 PMCR = PMCR_SF; in simpad_power_off()
Dgeneric.c94 PMCR = PMCR_SF; in sa1100_power_off()
/arch/arm/mach-pxa/include/mach/
Dpxa3xx-regs.h26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ macro
Dpxa2xx-regs.h20 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ macro
/arch/arm/mach-pxa/
Dzeus.c937 PMCR = PSPR = 0; in zeus_map_io()
Dtosa.c944 PMCR = 0x01; in tosa_init()
Dspitz.c988 PMCR = 0x00; in spitz_init()
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h884 #define PMCR __REG(0x90020000) /* PM Control Reg. */ macro