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Searched refs:R1 (Results 1 – 25 of 47) sorted by relevance

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/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S34 #define R1 %rbx macro
206 pushq R1
215 movq (R3), R1
217 input_whitening(R1,%r11,a_offset)
221 shr $32, R1
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
[all …]
Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
Dpoly1305-x86_64-cryptogams.pl2208 my ($R0,$R1,$R2,$R3,$R4, $S1,$S2,$S3,$S4) = map("%zmm$_",(16..24));
2251 vmovdqu `16*1-64`($ctx),%x#$D1 # will become ... ${R1}
2262 vpermd $D1,$T2,$R1
2268 vmovdqu64 $R1,0x00(%rsp,%rax){%k2}
2269 vpsrlq \$32,$R1,$T1
2292 vpmuludq $T0,$R1,$D1 # d1 = r0'*r1
2300 vpmuludq $T1,$R1,$M2
2312 vpmuludq $T2,$R1,$M3
2324 vpmuludq $T3,$R1,$M4
2401 vpermd $R1,$M0,$R1
[all …]
/arch/arm/crypto/
Dpoly1305-armv4.pl495 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
532 vdup.32 $R1,r3
555 vmull.u32 $D1,$R1,${R0}[1]
561 vmlal.u32 $D1,$R0,${R1}[1]
562 vmlal.u32 $D2,$R1,${R1}[1]
563 vmlal.u32 $D3,$R2,${R1}[1]
564 vmlal.u32 $D4,$R3,${R1}[1]
568 vmlal.u32 $D3,$R1,${R2}[1]
576 vmlal.u32 $D4,$R1,${R3}[1]
579 vmlal.u32 $D0,$R1,${S4}[1]
[all …]
/arch/arm64/crypto/
Dpoly1305-armv8.pl262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
513 ld1 {$R0,$R1,$S1,$R2},[x15],#64
575 umull $ACC1,$IN23_0,${R1}[2]
589 umlal $ACC2,$IN23_1,${R1}[2]
598 umlal $ACC3,$IN23_2,${R1}[2]
607 umlal $ACC4,$IN23_3,${R1}[2]
636 umlal $ACC3,$IN01_2,${R1}[0]
658 umlal $ACC1,$IN01_0,${R1}[0]
669 umlal $ACC2,$IN01_1,${R1}[0]
680 umlal $ACC4,$IN01_3,${R1}[0]
[all …]
/arch/hexagon/kernel/
Dvm_entry.S207 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
214 memd(R29 + #_PT_ER_VMEL) = R1:0; \
216 R1.L = #LO(CHandler); \
220 R1.H = #HI(CHandler); \
230 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
239 R1:0 = G1:0; \
241 memd(R29 + #_PT_ER_VMEL) = R1:0; \
242 R1 = # ## #(CHandler); \
302 R1 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS); define
321 R1:0 = memd(R29 + #_PT_ER_VMEL);
[all …]
Dvm_switch.S58 R29 = memw(R1 + #(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP));
75 THREADINFO_REG = memw(R1 + #_TASK_THREAD_INFO);
Dhead.S95 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
96 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
153 memw(R1 ++ #4) = R0
/arch/sparc/net/
Dbpf_jit_comp_32.c261 #define emit_cmp(R1, R2) \ argument
262 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
264 #define emit_cmpi(R1, IMM) \ argument
265 *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
267 #define emit_btst(R1, R2) \ argument
268 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
270 #define emit_btsti(R1, IMM) \ argument
271 *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
273 #define emit_sub(R1, R2, R3) \ argument
274 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
[all …]
/arch/powerpc/lib/
Dldstfp.S168 STXVD2X(0,R1,R8)
175 LXVD2X(0,R1,R8)
193 STXVD2X(0,R1,R8)
199 LXVD2X(0,R1,R8)
/arch/arm/boot/dts/
Dimx6qdl-gw552x.dtsi286 /* VDD_SOC (1+R1/R2 = 1.635) */
297 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
308 /* VDD_ARM (1+R1/R2 = 1.635) */
319 /* VDD_DDR (1+R1/R2 = 2.105) */
330 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
340 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw51xx.dtsi294 /* VDD_SOC (1+R1/R2 = 1.635) */
305 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
316 /* VDD_ARM (1+R1/R2 = 1.635) */
327 /* VDD_DDR (1+R1/R2 = 2.105) */
338 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
348 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dsun7i-a20-linutronix-testbox-v2.dts11 model = "Lamobo R1";
Dimx6qdl-gw52xx.dtsi365 /* VDD_SOC (1+R1/R2 = 1.635) */
376 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
387 /* VDD_ARM (1+R1/R2 = 1.635) */
398 /* VDD_DDR (1+R1/R2 = 2.105) */
409 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
427 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw53xx.dtsi362 /* VDD_SOC (1+R1/R2 = 1.635) */
373 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
384 /* VDD_ARM (1+R1/R2 = 1.635) */
395 /* VDD_DDR (1+R1/R2 = 2.105) */
406 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
424 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw551x.dtsi355 /* VDD_SOC (1+R1/R2 = 1.635) */
366 /* VDD_DDR (1+R1/R2 = 2.105) */
377 /* VDD_ARM (1+R1/R2 = 1.635) */
388 /* VDD_3P3 (1+R1/R2 = 1.281) */
399 /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
417 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw553x.dtsi341 /* VDD_SOC (1+R1/R2 = 1.635) */
352 /* VDD_DDR (1+R1/R2 = 2.105) */
363 /* VDD_ARM (1+R1/R2 = 1.635) */
374 /* VDD_3P3 (1+R1/R2 = 1.281) */
385 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
403 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw5904.dtsi406 /* VDD_SOC (1+R1/R2 = 1.635) */
417 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
428 /* VDD_ARM (1+R1/R2 = 1.635) */
439 /* VDD_DDR (1+R1/R2 = 2.105) */
450 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
460 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dsun8i-h2-plus-orangepi-r1.dts43 /* Orange Pi R1 is based on Orange Pi Zero design */
47 model = "Xunlong Orange Pi R1";
Dimx6qdl-gw5903.dtsi375 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
386 /* VDD_DDR (1+R1/R2 = 2.105) */
397 /* VDD_ARM (1+R1/R2 = 1.635) */
409 /* VDD_SOC (1+R1/R2 = 1.635) */
421 /* VDD_1P0 (1+R1/R2 = 1.38): */
431 /* VDD_HIGH (1+R1/R2 = 4.17) */
/arch/s390/crypto/
Dcrc32le-vx.S64 .quad 0x1c6e41596, 0x154442bd4 # R2, R1
72 .quad 0x09e4addf8, 0x740eef02 # R2, R1
/arch/parisc/kernel/
Dunaligned.c107 #define R1(i) (((i)>>21)&0x1f) macro
438 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned()
654 if (ret == 0 && modify && R1(regs->iir)) in handle_unaligned()
655 regs->gr[R1(regs->iir)] = newbase; in handle_unaligned()
/arch/mips/include/asm/
Dmipsregs.h1328 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \ argument
1329 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1330 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1335 #define _ASM_MACRO_2R(OP, R1, R2, ENC) \ argument
1336 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1337 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1343 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \ argument
1344 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1345 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1352 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \ argument
[all …]
/arch/mips/bcm47xx/
DKconfig20 This will generate an image with support for SSB and MIPS32 R1 instruction set.
/arch/mips/loongson64/
DPlatform10 # as MIPS64 R2; older versions as just R1. This leaves the possibility open

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