Searched refs:R11 (Results 1 – 23 of 23) sorted by relevance
| /arch/hexagon/kernel/ |
| D | vm_entry.S | 51 { memd(R0 + #_PT_R1110) = R11:10; \
60 R11 = m1; \
68 { memd(R0 + #_PT_M1M0) = R11:10; \
96 { memd(R0 + #_PT_R1110) = R11:10; \
104 R11:10 = C7:6; }\
108 { memd(R0 + #_PT_M1M0) = R11:10; \
128 { R11:10 = memd(R0 + #_PT_M1M0); \
133 m1 = R11; } \
142 { R11:10 = memd(R0 + #_PT_R1110); \
162 { R11:10 = memd(R0 + #_PT_M1M0); \
[all …]
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| /arch/x86/um/ |
| D | ptrace_64.c | 27 [R11 >> 3] = HOST_R11,
59 case R11: in putreg()
137 case R11: in getreg()
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| D | user-offsets.c | 57 DEFINE_LONGS(HOST_R11, R11); in foo()
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| D | signal.c | 188 GETREG(R11, r11); in copy_sc_from_user()
265 PUTREG(R11, r11); in copy_sc_to_user()
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| /arch/x86/include/uapi/asm/ |
| D | ptrace-abi.h | 40 #define R11 48 macro
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| /arch/powerpc/platforms/powernv/ |
| D | opal-wrappers.S | 37 ld r0,STK_PARAM(R11)(r1)
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| /arch/powerpc/kernel/ |
| D | module_64.c | 135 PPC_INST_ADDIS | __PPC_RT(R11) | __PPC_RA(R2),
136 PPC_INST_ADDI | __PPC_RT(R11) | __PPC_RA(R11),
139 PPC_INST_LD | __PPC_RT(R12) | __PPC_RA(R11) | 32,
142 PPC_INST_LD | __PPC_RT(R2) | __PPC_RA(R11) | 40,
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| /arch/x86/um/os-Linux/ |
| D | mcontext.c | 22 COPY(R8); COPY(R9); COPY(R10); COPY(R11); in get_regs_from_mc()
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| /arch/powerpc/platforms/pseries/ |
| D | hvCall.S | 247 ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
283 ld r10,STACK_FRAME_OVERHEAD+STK_PARAM(R11)(r1)
324 ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
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| /arch/x86/kvm/ |
| D | kvm_cache_regs.h | 33 BUILD_KVM_GPR_ACCESSORS(r11, R11) in BUILD_KVM_GPR_ACCESSORS()
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| /arch/powerpc/kvm/ |
| D | bookehv_interrupts.S | 199 PPC_STL r8, VCPU_GPR(R11)(r4)
293 PPC_STL r4, VCPU_GPR(R11)(r11)
328 PPC_STL r4, VCPU_GPR(R11)(r11)
646 PPC_LL r11, VCPU_GPR(R11)(r4)
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| D | booke_interrupts.S | 211 stw r11, VCPU_GPR(R11)(r4)
419 lwz r11, VCPU_GPR(R11)(r4)
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| D | book3s_hv_rmhandlers.S | 1105 ld r11, VCPU_GPR(R11)(r4)
1306 std r11, VCPU_GPR(R11)(r9)
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| /arch/x86/kernel/ |
| D | ftrace_64.S | 196 movq %r11, R11(%rsp)
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| /arch/x86/entry/ |
| D | calling.h | 79 #define R11 6*8 macro
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| D | entry_64.S | 164 movq R11(%rsp), %r11
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| /arch/arm/mach-tegra/ |
| D | reset-handler.S | 182 mov r11, r11, lsl r10 @ R11 = CPU mask
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| /arch/arm/boot/dts/ |
| D | gemini-sl93512r.dts | 224 "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
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| D | gemini-dlink-dns-313.dts | 251 "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
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| /arch/hexagon/lib/ |
| D | memcpy.S | 142 #define dataF8 R11:10 /* hi 8 bytes of non-aligned transfer */
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| /arch/ia64/kernel/ |
| D | entry.S | 712 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
718 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
864 ld8.fill r11=[r2],PT(R18)-PT(R11)
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| D | ivt.S | 949 add r17=PT(R11),r1 // initialize second base pointer
955 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
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| /arch/x86/lib/ |
| D | x86-opcode-map.txt | 555 cb: BSWAP RBX/EBX/R11/R11D
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