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Searched refs:TSB (Results 1 – 4 of 4) sorted by relevance

/arch/sparc/include/asm/
Dtsb.h77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
78 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
86 661: lduwa [TSB] ASI_N, REG; \
89 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
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/arch/sparc/kernel/
Ddtlb_miss.S3 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
Ditlb_miss.S3 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
9 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
/arch/arm64/
DKconfig703 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
709 Affected cores may fail to flush the trace data on a TSB instruction, when
713 Workaround is to issue two TSB consecutively on affected cores.
718 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
724 Affected cores may fail to flush the trace data on a TSB instruction, when
728 Workaround is to issue two TSB consecutively on affected cores.