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Searched refs:cpuinfo (Results 1 – 25 of 33) sorted by relevance

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/arch/nios2/kernel/
Dcpuinfo.c17 struct cpuinfo cpuinfo; variable
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
50 strlcpy(cpuinfo.cpu_impl, str, sizeof(cpuinfo.cpu_impl)); in setup_cpuinfo()
52 strcpy(cpuinfo.cpu_impl, "<unknown>"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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Dsetup.c183 copy_exception_handler(cpuinfo.exception_addr); in setup_arch()
187 copy_fast_tlb_miss_handler(cpuinfo.fast_tlb_miss_exc_addr); in setup_arch()
DMakefile9 obj-y += cpuinfo.o
Dprocess.c46 pr_notice("Machine restart (%08x)...\n", cpuinfo.reset_addr); in machine_restart()
51 : "r" (cpuinfo.reset_addr) in machine_restart()
/arch/microblaze/kernel/cpu/
Dmb.c36 if (cpuinfo.fpga_family_code == family_string_lookup[i].k) { in show_cpuinfo()
44 if (cpuinfo.ver_code == cpu_ver_lookup[i].k) { in show_cpuinfo()
58 cpuinfo.endian ? "little" : "big", in show_cpuinfo()
59 cpuinfo.cpu_clock_freq / 1000000, in show_cpuinfo()
60 cpuinfo.cpu_clock_freq % 1000000, in show_cpuinfo()
69 (cpuinfo.use_instr & PVR0_USE_BARREL_MASK) ? "yes" : "no", in show_cpuinfo()
70 (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) ? "yes" : "no", in show_cpuinfo()
71 (cpuinfo.use_instr & PVR2_USE_PCMP_INSTR) ? "yes" : "no", in show_cpuinfo()
72 (cpuinfo.use_instr & PVR0_USE_DIV_MASK) ? "yes" : "no"); in show_cpuinfo()
74 seq_printf(m, " MMU:\t\t%x\n", cpuinfo.mmu); in show_cpuinfo()
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Dcache.c169 cpuinfo.icache_line_length, cpuinfo.icache_size); in __flush_icache_range_msr_irq()
175 CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic); in __flush_icache_range_msr_irq()
177 for (i = start; i < end; i += cpuinfo.icache_line_length) in __flush_icache_range_msr_irq()
196 cpuinfo.icache_line_length, cpuinfo.icache_size); in __flush_icache_range_nomsr_irq()
202 CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic); in __flush_icache_range_nomsr_irq()
204 for (i = start; i < end; i += cpuinfo.icache_line_length) in __flush_icache_range_nomsr_irq()
223 cpuinfo.icache_line_length, cpuinfo.icache_size); in __flush_icache_range_noirq()
225 CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic); in __flush_icache_range_noirq()
227 for (i = start; i < end; i += cpuinfo.icache_line_length) in __flush_icache_range_noirq()
244 CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic); in __flush_icache_all_msr_irq()
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Dcpuinfo.c88 struct cpuinfo cpuinfo; variable
103 set_cpuinfo_static(&cpuinfo, cpu); in setup_cpuinfo()
110 set_cpuinfo_static(&cpuinfo, cpu); in setup_cpuinfo()
111 set_cpuinfo_pvr_full(&cpuinfo, cpu); in setup_cpuinfo()
115 set_cpuinfo_static(&cpuinfo, cpu); in setup_cpuinfo()
118 if (cpuinfo.mmu_privins) in setup_cpuinfo()
133 cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency"); in setup_cpuinfo_clk()
135 cpuinfo.cpu_clock_freq = clk_get_rate(clk); in setup_cpuinfo_clk()
138 if (!cpuinfo.cpu_clock_freq) { in setup_cpuinfo_clk()
DMakefile13 obj-y += cache.o cpuinfo.o cpuinfo-pvr-full.o cpuinfo-static.o mb.o pvr.o
Dcpuinfo-pvr-full.c28 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) in set_cpuinfo_pvr_full()
/arch/openrisc/kernel/
Dsetup.c102 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; in print_cpuinfo() local
108 version, revision, cpuinfo->clock_frequency / 1000000); in print_cpuinfo()
119 cpuinfo->dcache_size, cpuinfo->dcache_block_size, in print_cpuinfo()
120 cpuinfo->dcache_ways); in print_cpuinfo()
126 cpuinfo->icache_size, cpuinfo->icache_block_size, in print_cpuinfo()
127 cpuinfo->icache_ways); in print_cpuinfo()
176 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id]; in setup_cpuinfo() local
183 cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); in setup_cpuinfo()
185 cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); in setup_cpuinfo()
186 cpuinfo->icache_size = in setup_cpuinfo()
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Ddma.c28 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; in page_set_nocache() local
39 for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size) in page_set_nocache()
102 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; in arch_sync_dma_for_device() local
108 cl += cpuinfo->dcache_block_size) in arch_sync_dma_for_device()
114 cl += cpuinfo->dcache_block_size) in arch_sync_dma_for_device()
Dtime.c70 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu]; in openrisc_clockevent_init() local
85 clockevents_config_and_register(evt, cpuinfo->clock_frequency, in openrisc_clockevent_init()
151 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; in openrisc_timer_init() local
153 if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency)) in openrisc_timer_init()
/arch/mips/include/asm/
Dcpu-info.h151 static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo) in cpu_cluster() argument
157 return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >> in cpu_cluster()
161 static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo) in cpu_core() argument
163 return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >> in cpu_core()
167 static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo) in cpu_vpe_id() argument
173 return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >> in cpu_vpe_id()
177 extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
178 extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
179 extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
203 static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo) in cpu_asid_mask() argument
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/arch/nios2/mm/
Dcacheflush.c22 start &= ~(cpuinfo.dcache_line_size - 1); in __flush_dcache()
23 end += (cpuinfo.dcache_line_size - 1); in __flush_dcache()
24 end &= ~(cpuinfo.dcache_line_size - 1); in __flush_dcache()
26 if (end > start + cpuinfo.dcache_size) in __flush_dcache()
27 end = start + cpuinfo.dcache_size; in __flush_dcache()
29 for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { in __flush_dcache()
41 start &= ~(cpuinfo.dcache_line_size - 1); in __invalidate_dcache()
42 end += (cpuinfo.dcache_line_size - 1); in __invalidate_dcache()
43 end &= ~(cpuinfo.dcache_line_size - 1); in __invalidate_dcache()
45 for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { in __invalidate_dcache()
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Dtlb.c22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
136 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in flush_tlb_one()
173 line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2)); in dump_tlb_line()
180 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in dump_tlb_line()
212 for (i = 0; i < cpuinfo.tlb_num_lines; i++) in dump_tlb()
226 for (line = 0; line < cpuinfo.tlb_num_lines; line++) { in flush_tlb_pid()
229 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in flush_tlb_pid()
280 for (line = 0; line < cpuinfo.tlb_num_lines; line++) { in flush_tlb_all()
282 for (way = 0; way < cpuinfo.tlb_num_ways; way++) in flush_tlb_all()
Dmmu_context.c21 #define PID_BITS (cpuinfo.tlb_pid_num_bits)
/arch/microblaze/mm/
Dconsistent.c38 #define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
48 if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high) in arch_dma_set_uncached()
/arch/microblaze/include/asm/
Dcpuinfo.h30 struct cpuinfo { struct
87 extern struct cpuinfo cpuinfo; argument
93 void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
94 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
/arch/nios2/include/asm/
Dcpuinfo.h11 struct cpuinfo { struct
42 extern struct cpuinfo cpuinfo; argument
Dregisters.h48 #define TLBMISC_PID_MASK ((1UL << cpuinfo.tlb_pid_num_bits) - 1)
/arch/parisc/kernel/
Dtime.c68 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); in timer_interrupt() local
76 next_tick = cpuinfo->it_value; in timer_interrupt()
86 cpuinfo->it_value = next_tick; in timer_interrupt()
Dtopology.c80 const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); in store_cpu_topology() local
85 if (cpuinfo->cpu_loc == p->cpu_loc) { in store_cpu_topology()
Dprocessor.c385 const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); in show_cpuinfo() local
387 if (0 == cpuinfo->hpa) in show_cpuinfo()
/arch/powerpc/platforms/
DKconfig209 on-die temperature in /proc/cpuinfo if the cpu supports it.
212 don't assume the cpu temp is actually what /proc/cpuinfo says it is.
231 bound in /proc/cpuinfo. If the range is large, the temperature is
236 /proc/cpuinfo.
/arch/mips/kernel/
Dcpu-probe.c2140 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) in cpu_set_cluster() argument
2146 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; in cpu_set_cluster()
2147 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; in cpu_set_cluster()
2150 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) in cpu_set_core() argument
2155 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; in cpu_set_core()
2156 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; in cpu_set_core()
2159 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) in cpu_set_vpe_id() argument
2168 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; in cpu_set_vpe_id()
2169 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; in cpu_set_vpe_id()

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