Home
last modified time | relevance | path

Searched refs:cvmx_read_csr (Results 1 – 25 of 37) sorted by relevance

12

/arch/mips/cavium-octeon/executive/
Dcvmx-helper-xaui.c50 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); in __cvmx_helper_xaui_enumerate()
76 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_xaui_probe()
126 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); in __cvmx_helper_xaui_enable()
134 xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); in __cvmx_helper_xaui_enable()
139 gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); in __cvmx_helper_xaui_enable()
141 gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); in __cvmx_helper_xaui_enable()
143 pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); in __cvmx_helper_xaui_enable()
149 gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); in __cvmx_helper_xaui_enable()
156 xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); in __cvmx_helper_xaui_enable()
183 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); in __cvmx_helper_xaui_enable()
[all …]
Dcvmx-l2c.c58 return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff; in cvmx_l2c_get_core_way_partition()
73 return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition()
75 return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition()
77 return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition()
79 return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field; in cvmx_l2c_get_core_way_partition()
120 (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition()
125 (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition()
130 (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition()
135 (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) | in cvmx_l2c_set_core_way_partition()
157 (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); in cvmx_l2c_set_hw_way_partition()
[all …]
Dcvmx-helper-sgmii.c60 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
70 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
72 cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
98 cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
108 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
113 cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG in __cvmx_helper_sgmii_hardware_init_one_time()
150 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link()
211 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed()
230 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed()
237 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_link_speed()
[all …]
Dcvmx-helper-rgmii.c56 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_rgmii_probe()
113 tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); in cvmx_helper_rgmii_internal_loopback()
115 tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); in cvmx_helper_rgmii_internal_loopback()
117 tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); in cvmx_helper_rgmii_internal_loopback()
168 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_rgmii_enable()
203 cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL in __cvmx_helper_rgmii_enable()
243 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); in __cvmx_helper_rgmii_enable()
270 asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); in __cvmx_helper_rgmii_link_get()
314 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_rgmii_link_set()
319 cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & in __cvmx_helper_rgmii_link_set()
[all …]
Dcvmx-helper.c97 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_cn68xx()
111 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface)); in __cvmx_get_mode_cn68xx()
123 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3)); in __cvmx_get_mode_cn68xx()
128 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_cn68xx()
170 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2()
172 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_octeon2()
189 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2()
197 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2()
208 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2()
218 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_get_mode_octeon2()
[all …]
Dcvmx-spi.c207 spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); in cvmx_spi_reset_cb()
209 stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); in cvmx_spi_reset_cb()
219 spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); in cvmx_spi_reset_cb()
249 cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); in cvmx_spi_reset_cb()
252 cvmx_read_csr(CVMX_STXX_INT_REG(interface))); in cvmx_spi_reset_cb()
449 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_clock_detect_cb()
474 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_clock_detect_cb()
533 spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); in cvmx_spi_training_cb()
548 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); in cvmx_spi_training_cb()
586 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); in cvmx_spi_calendar_sync_cb()
[all …]
Dcvmx-helper-jtag.c70 cvmx_read_csr(CVMX_CIU_QLM_JTGC); in cvmx_helper_qlm_jtag_init()
98 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); in cvmx_helper_qlm_jtag_shift()
142 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); in cvmx_helper_qlm_jtag_update()
Dcvmx-helper-loop.c59 port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_loop_probe()
66 ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); in __cvmx_helper_loop_probe()
Dcvmx-cmd-queue.c169 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); in cvmx_cmd_queue_initialize()
264 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); in cvmx_cmd_queue_length()
268 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); in cvmx_cmd_queue_length()
280 cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS in cvmx_cmd_queue_length()
Dcvmx-helper-util.c189 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); in __cvmx_helper_setup_gmx()
209 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); in __cvmx_helper_setup_gmx()
218 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); in __cvmx_helper_setup_gmx()
252 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); in __cvmx_helper_setup_gmx()
Docteon-model.c47 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) in cvmx_fuse_read_byte()
74 l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3; in octeon_model_get_string_buffer()
75 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); in octeon_model_get_string_buffer()
76 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); in octeon_model_get_string_buffer()
413 if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32)) in octeon_model_get_string_buffer()
Dcvmx-interrupt-rsl.c65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); in __cvmx_interrupt_asxx_enable()
83 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_interrupt_gmxx_enable()
Dcvmx-interrupt-decodes.c55 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); in __cvmx_interrupt_gmxx_rxx_int_en_enable()
236 cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); in __cvmx_interrupt_pcsx_intx_en_reg_enable()
277 cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); in __cvmx_interrupt_pcsxx_int_en_reg_enable()
307 cvmx_read_csr(CVMX_SPXX_INT_REG(index))); in __cvmx_interrupt_spxx_int_msk_enable()
346 cvmx_read_csr(CVMX_STXX_INT_REG(index))); in __cvmx_interrupt_stxx_int_msk_enable()
Dcvmx-helper-spi.c87 enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); in __cvmx_helper_spi_probe()
116 port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_spi_enable()
Dcvmx-helper-npi.c91 cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); in __cvmx_helper_npi_enable()
/arch/mips/include/asm/octeon/
Dcvmx-ipd.h117 ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_config()
132 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_enable()
151 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_disable()
166 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); in cvmx_ipd_free_ptr()
171 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_free_ptr()
180 cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); in cvmx_ipd_free_ptr()
197 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); in cvmx_ipd_free_ptr()
207 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); in cvmx_ipd_free_ptr()
230 cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); in cvmx_ipd_free_ptr()
242 cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); in cvmx_ipd_free_ptr()
[all …]
Dcvmx-pip.h389 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); in cvmx_pip_get_port_status()
390 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); in cvmx_pip_get_port_status()
391 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); in cvmx_pip_get_port_status()
392 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); in cvmx_pip_get_port_status()
393 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); in cvmx_pip_get_port_status()
394 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); in cvmx_pip_get_port_status()
395 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); in cvmx_pip_get_port_status()
396 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); in cvmx_pip_get_port_status()
397 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); in cvmx_pip_get_port_status()
398 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); in cvmx_pip_get_port_status()
[all …]
Dcvmx.h291 static inline uint64_t cvmx_read_csr(uint64_t csr_addr) in cvmx_read_csr() function
299 return cvmx_read_csr((__force uint64_t) csr_addr); in cvmx_readq_csr()
386 return cvmx_read_csr(node_addr); in cvmx_read_csr_node()
465 c.u64 = cvmx_read_csr(address); \
491 ciu_fuse = cvmx_read_csr(ciu_fuse_reg); in cvmx_octeon_num_cores()
Dcvmx-fpa.h148 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); in cvmx_fpa_enable()
163 cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); in cvmx_fpa_enable()
188 cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); in cvmx_fpa_alloc()
Dcvmx-pko.h588 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); in cvmx_pko_get_port_status()
595 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); in cvmx_pko_get_port_status()
606 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); in cvmx_pko_get_port_status()
612 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); in cvmx_pko_get_port_status()
/arch/mips/cavium-octeon/
Docteon-usb.c254 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); in dwc3_octeon_config_power()
259 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); in dwc3_octeon_config_power()
264 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); in dwc3_octeon_config_power()
271 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); in dwc3_octeon_config_power()
277 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); in dwc3_octeon_config_power()
359 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
366 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
377 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
381 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
388 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
[all …]
Dcsrc-octeon.c45 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); in octeon_setup_delays()
52 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); in octeon_setup_delays()
86 u64 clk_count = cvmx_read_csr(clk_reg); in octeon_init_cvmcount()
Docteon-irq.c1302 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); in octeon_irq_ip2_ciu()
1319 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); in octeon_irq_ip3_ciu()
1337 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid)); in octeon_irq_ip4_ciu()
1338 u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid)); in octeon_irq_ip4_ciu()
1403 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); in octeon_irq_init_ciu_percpu()
1425 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); in octeon_irq_init_ciu2_percpu()
1986 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; in octeon_irq_ciu2()
1993 src = cvmx_read_csr(src_reg); in octeon_irq_ciu2()
2012 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); in octeon_irq_ciu2()
2014 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id)); in octeon_irq_ciu2()
[all …]
/arch/mips/pci/
Dpcie-octeon.c179 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); in cvmx_pcie_cfgx_read()
186 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port)); in cvmx_pcie_cfgx_read()
436 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); in __cvmx_pcie_rc_initialize_config_space()
456 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
463 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
594 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); in __cvmx_pcie_rc_initialize_link_gen1()
622 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); in __cvmx_pcie_rc_initialize_link_gen1()
645 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); in __cvmx_pcie_rc_initialize_link_gen1()
712 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); in __cvmx_pcie_rc_initialize_gen1()
723 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); in __cvmx_pcie_rc_initialize_gen1()
[all …]
Dmsi-octeon.c276 en = cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_enable_pcie()
279 cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_enable_pcie()
292 en = cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_disable_pcie()
295 cvmx_read_csr(mis_ena_reg[irq_index]); in octeon_irq_msi_disable_pcie()
352 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \

12