Searched refs:dcr (Results 1 – 25 of 34) sorted by relevance
12
86 unsigned long dcr; in dmabrg_irq() local89 dcr = __raw_readl(DMABRGCR); in dmabrg_irq()90 __raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ in dmabrg_irq()91 dcr &= dcr >> 8; /* ignore masked */ in dmabrg_irq()94 if (dcr & 1) in dmabrg_irq()96 if (dcr & 2) in dmabrg_irq()100 dcr >>= 16; in dmabrg_irq()101 while (dcr) { in dmabrg_irq()102 i = __ffs(dcr); in dmabrg_irq()103 dcr &= dcr - 1; in dmabrg_irq()[all …]
39 dcr = 1 define41 mfdcr r3,dcr; blr42 mtdcr dcr,r4; blr43 dcr = dcr + 1 define
19 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";68 dcr-reg = <0x2c0 0x8>;81 dcr-reg = <0x2c8 0x8>;95 dcr-reg = <0x350 0x8>;109 dcr-reg = <0x358 0x8>;123 dcr-reg = <0x360 0x8>;136 dcr-reg = <0x368 0x8>;149 dcr-reg = <0x370 0x8>;[all …]
24 dcr-parent = <&{/cpus/cpu@0}>;44 dcr-controller;45 dcr-access-method = "native";58 dcr-controller;59 dcr-access-method = "native";74 dcr-controller;75 dcr-access-method = "native";90 dcr-controller;91 dcr-access-method = "native";107 dcr-reg = <0xffc00000 0x00030000>;
16 dcr-parent = <&{/cpus/cpu@0}>;37 dcr-controller;38 dcr-access-method = "native";51 dcr-reg = <0x0c0 0x010>;61 dcr-reg = <0x0d0 0x010>;73 dcr-reg = <0x0e0 0x010>;85 dcr-reg = <0x0f0 0x010>;102 dcr-reg = <0x010 0x002>;107 dcr-reg = <0x180 0x062>;128 dcr-reg = <0x100 0x020>;
19 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";54 dcr-reg = <0x0c0 0x009>;64 dcr-reg = <0x0d0 0x009>;74 dcr-reg = <0x00e 0x002>;79 dcr-reg = <0x00c 0x002>;91 dcr-reg = <0x010 0x002>;96 dcr-reg = <0x100 0x027>;101 dcr-reg = <0x180 0x062>;[all …]
20 dcr-parent = <&{/cpus/cpu@0}>;43 dcr-controller;44 dcr-access-method = "native";58 dcr-reg = <0x200 0x009>;69 dcr-reg = <0x0c0 0x009>;82 dcr-reg = <0x0d0 0x009>;94 dcr-reg = <0x210 0x009>;105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */128 dcr-reg = <0x010 0x002>;[all …]
16 dcr-parent = <&{/cpus/cpu@0}>;38 dcr-controller;39 dcr-access-method = "native";53 dcr-reg = <0x0c0 0x009>;63 dcr-reg = <0x0d0 0x009>;75 dcr-reg = <0x0e0 0x009>;87 dcr-reg = <0x0f0 0x009>;105 dcr-reg = <0x00e 0x002>;110 dcr-reg = <0x00c 0x002>;115 dcr-reg = <0x020 0x008[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";56 dcr-reg = <0x0c0 0x009>;66 dcr-reg = <0x0d0 0x009>;78 dcr-reg = <0x0e0 0x009>;90 dcr-reg = <0x0f0 0x009>;100 dcr-reg = <0x00e 0x002>;105 dcr-reg = <0x00c 0x002>;110 dcr-reg = <0x040 0x020>;[all …]
24 dcr-parent = <&{/cpus/cpu@0}>;47 dcr-controller;48 dcr-access-method = "native";62 dcr-reg = <0x0c0 0x009>;72 dcr-reg = <0x0d0 0x009>;84 dcr-reg = <0x0e0 0x009>;96 dcr-reg = <0x0f0 0x009>;106 dcr-reg = <0x00e 0x002>;111 dcr-reg = <0x00c 0x002>;116 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */[all …]
22 dcr-parent = <&{/cpus/cpu@0}>;45 dcr-controller;46 dcr-access-method = "native";59 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x0d0 0x009>;81 dcr-reg = <0x0e0 0x009>;91 dcr-access-method = "native";92 dcr-reg = <0x0b0 0x003>;107 dcr-reg = <0x010 0x002>;122 dcr-reg = <0x180 0x062>;[all …]
21 dcr-parent = <&{/cpus/cpu@0}>;44 dcr-controller;45 dcr-access-method = "native";58 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x0d0 0x009>;79 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;92 dcr-reg = <0x010 0x002>;98 dcr-reg = <0x020 0x008 0x00a 0x001>;104 dcr-reg = <0x100 0x027>;109 dcr-reg = <0x180 0x062>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";53 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x380 0x62>;88 dcr-reg = <0x0a 0x05>;180 dcr-reg = <0xe0 0x9>;214 dcr-reg = <0x12 0x2>;
18 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";54 dcr-reg = <0x0c0 0x009>;64 dcr-reg = <0x0d0 0x009>;76 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x010 0x002>;101 dcr-reg = <0x180 0x062>;124 dcr-reg = <0x0a0 0x005>;129 dcr-reg = <0x012 0x002>;[all …]
47 dcr-controller;48 dcr-access-method = "native";61 dcr-reg = <0x0c0 9>;71 dcr-reg = <0x0d0 9>;81 dcr-reg = <0x00e 2>;86 dcr-reg = <0x00c 2>;98 dcr-reg = <0x010 2>;103 dcr-reg = <0x100 0x027>;108 dcr-reg = <0x180 0x062>;138 dcr-reg = <0x012 2>;
18 dcr-parent = <&{/cpus/cpu@0}>;39 dcr-controller;40 dcr-access-method = "native";53 dcr-reg = <0x0c0 0x009>;63 dcr-reg = <0x0d0 0x009>;75 dcr-reg = <0x0e0 0x009>;87 dcr-reg = <0x0f0 0x009>;97 dcr-reg = <0x00e 0x002>;102 dcr-reg = <0x00c 0x002>;114 dcr-reg = <0x010 0x002>;[all …]
22 dcr-parent = <&{/cpus/cpu@0}>;47 dcr-controller;48 dcr-access-method = "native";61 dcr-reg = <0x0c0 0x009>;71 dcr-reg = <0x0d0 0x009>;83 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x00e 0x002>;98 dcr-reg = <0x00c 0x002>;110 dcr-reg = <0x010 0x002>;115 dcr-reg = <0x100 0x027>;[all …]
22 dcr-parent = <&{/cpus/cpu@0}>;42 dcr-controller;43 dcr-access-method = "native";56 dcr-reg = <0x0c0 0x009>;67 dcr-reg = <0x0d0 0x009>;
22 dcr-parent = <&{/cpus/cpu@0}>;45 dcr-controller;46 dcr-access-method = "native";60 dcr-reg = <0x0c0 0x009>;70 dcr-reg = <0x0d0 0x009>;82 dcr-reg = <0x0e0 0x009>;94 dcr-reg = <0x0f0 0x009>;104 dcr-reg = <0x00e 0x002>;109 dcr-reg = <0x00c 0x002>;114 dcr-reg = <0x040 0x020>;[all …]
19 dcr-parent = <&{/cpus/cpu@0}>;44 dcr-controller;45 dcr-access-method = "native";58 dcr-reg = <0x0c0 0x009>;68 dcr-reg = <0x0d0 0x009>;78 dcr-reg = <0x00e 0x002>;83 dcr-reg = <0x00c 0x002>;95 dcr-reg = <0x010 0x002>;100 dcr-reg = <0x100 0x027>;105 dcr-reg = <0x180 0x062>;[all …]
21 dcr-parent = <&{/cpus/cpu@0}>;46 dcr-controller;47 dcr-access-method = "native";60 dcr-reg = <0x0c0 0x009>;70 dcr-reg = <0x0d0 0x009>;80 dcr-reg = <0x00e 0x002>;85 dcr-reg = <0x00c 0x002>;97 dcr-reg = <0x010 0x002>;102 dcr-reg = <0x100 0x027>;107 dcr-reg = <0x180 0x062>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";55 dcr-reg = <0x0c0 0x009>;65 dcr-reg = <0x0d0 0x009>;77 dcr-reg = <0x0e0 0x009>;94 dcr-reg = <0x010 0x002>;102 dcr-reg = <0x180 0x062>;125 dcr-reg = <0x0a0 0x005>;130 dcr-reg = <0x012 0x002>;[all …]
22 dcr-parent = <&{/cpus/cpu@0}>;47 dcr-controller;48 dcr-access-method = "native";61 dcr-reg = <0x0c0 0x009>;71 dcr-reg = <0x0d0 0x009>;83 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x00e 0x002>;98 dcr-reg = <0x00c 0x002>;110 dcr-reg = <0x010 0x002>;127 dcr-reg = <0x100 0x027>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;43 dcr-controller;44 dcr-access-method = "native";57 dcr-reg = <0x0c0 0x009>;67 dcr-reg = <0x0d0 0x009>;79 dcr-reg = <0x0e0 0x009>;91 dcr-reg = <0x0f0 0x009>;101 dcr-reg = <0x00e 0x002>;106 dcr-reg = <0x00c 0x002>;118 dcr-reg = <0x010 0x002>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";55 dcr-reg = <0x0c0 0x009>;65 dcr-reg = <0x0d0 0x009>;77 dcr-reg = <0x0e0 0x009>;87 dcr-access-method = "native";88 dcr-reg = <0x0b0 0x003>;103 dcr-reg = <0x010 0x002>;118 dcr-reg = <0x180 0x062>;[all …]