| /arch/nds32/mm/ |
| D | proc.c | 103 unsigned long end, line_size; in cpu_icache_inval_all() local
106 end = in cpu_icache_inval_all()
110 end -= line_size; in cpu_icache_inval_all()
111 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
112 end -= line_size; in cpu_icache_inval_all()
113 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
114 end -= line_size; in cpu_icache_inval_all()
115 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
116 end -= line_size; in cpu_icache_inval_all()
117 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
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| /arch/mips/pci/ |
| D | pci-malta.c | 31 .end = 0x000fffffUL,
81 resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; in mips_pcibios_init() local
104 end = GT_READ(GT_PCI0M0HD_OFS); in mips_pcibios_init()
106 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); in mips_pcibios_init()
112 if (end1 - start1 > end - start) { in mips_pcibios_init()
114 end = end1; in mips_pcibios_init()
117 mask = ~(start ^ end); in mips_pcibios_init()
122 gt64120_mem_resource.end = end; in mips_pcibios_init()
126 gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; in mips_pcibios_init()
127 gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; in mips_pcibios_init()
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| /arch/csky/mm/ |
| D | cachev2.c | 24 void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
28 for (; i < end; i += L1_CACHE_BYTES) in icache_inv_range()
35 unsigned long end; member
54 for (; i < param->end; i += L1_CACHE_BYTES) in local_icache_inv_range()
62 void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
64 struct cache_range param = { start, end }; in icache_inv_range()
79 void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument
83 for (; i < end; i += L1_CACHE_BYTES) in dcache_wb_range()
88 void cache_wbinv_range(unsigned long start, unsigned long end) in cache_wbinv_range() argument
90 dcache_wb_range(start, end); in cache_wbinv_range()
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| D | cachev1.c | 45 unsigned int end, in cache_op_range() argument
53 if (unlikely((end - start) >= PAGE_SIZE) || in cache_op_range()
68 for (; i < end; i += L1_CACHE_BYTES) { in cache_op_range()
87 void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
89 cache_op_range(start, end, INS_CACHE|CACHE_INV, 0); in icache_inv_range()
102 void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument
104 cache_op_range(start, end, DATA_CACHE|CACHE_CLR, 0); in dcache_wb_range()
112 void cache_wbinv_range(unsigned long start, unsigned long end) in cache_wbinv_range() argument
114 cache_op_range(start, end, INS_CACHE|DATA_CACHE|CACHE_CLR|CACHE_INV, 0); in cache_wbinv_range()
123 void dma_wbinv_range(unsigned long start, unsigned long end) in dma_wbinv_range() argument
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| /arch/microblaze/kernel/cpu/ |
| D | cache.c | 92 #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size) \ argument
96 end = min(start + cache_size, end); \
125 #define CACHE_RANGE_LOOP_2(start, end, line_length, op) \ argument
130 end = ((end & align) == end) ? end - line_length : end & align; \
131 count = end - start; \
142 #define CACHE_RANGE_LOOP_1(start, end, line_length, op) \ argument
146 end = ((end & align) == end) ? end - line_length : end & align; \
147 WARN_ON(end < start); \
153 : : "r" (temp), "r" (start), "r" (end), \
159 static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end) in __flush_icache_range_msr_irq() argument
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| /arch/nios2/mm/ |
| D | cacheflush.c | 18 static void __flush_dcache(unsigned long start, unsigned long end) in __flush_dcache() argument
23 end += (cpuinfo.dcache_line_size - 1); in __flush_dcache()
24 end &= ~(cpuinfo.dcache_line_size - 1); in __flush_dcache()
26 if (end > start + cpuinfo.dcache_size) in __flush_dcache()
27 end = start + cpuinfo.dcache_size; in __flush_dcache()
29 for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { in __flush_dcache()
37 static void __invalidate_dcache(unsigned long start, unsigned long end) in __invalidate_dcache() argument
42 end += (cpuinfo.dcache_line_size - 1); in __invalidate_dcache()
43 end &= ~(cpuinfo.dcache_line_size - 1); in __invalidate_dcache()
45 for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { in __invalidate_dcache()
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| D | ioremap.c | 26 unsigned long end; in remap_area_pte() local
32 end = address + size; in remap_area_pte()
33 if (end > PMD_SIZE) in remap_area_pte()
34 end = PMD_SIZE; in remap_area_pte()
35 if (address >= end) in remap_area_pte()
47 } while (address && (address < end)); in remap_area_pte()
54 unsigned long end; in remap_area_pmd() local
57 end = address + size; in remap_area_pmd()
58 if (end > PGDIR_SIZE) in remap_area_pmd()
59 end = PGDIR_SIZE; in remap_area_pmd()
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| /arch/x86/pci/ |
| D | amd_bus.c | 72 u64 end; in early_root_info_init() local
161 end = (reg & 0xfff000) | 0xfff; in early_root_info_init()
168 node, link, start, end); in early_root_info_init()
171 if (end > 0xffff) in early_root_info_init()
172 end = 0xffff; in early_root_info_init()
173 update_res(info, start, end, IORESOURCE_IO, 1); in early_root_info_init()
174 subtract_range(range, RANGE_NUM, start, end + 1); in early_root_info_init()
181 if (!range[i].end) in early_root_info_init()
184 update_res(info, range[i].start, range[i].end - 1, in early_root_info_init()
191 end = cap_resource((0xfdULL<<32) - 1); in early_root_info_init()
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| /arch/c6x/include/asm/ |
| D | cache.h | 63 extern void enable_caching(unsigned long start, unsigned long end);
64 extern void disable_caching(unsigned long start, unsigned long end);
77 extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
78 extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
80 unsigned int end);
81 extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
82 extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
83 extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
85 unsigned int end);
87 unsigned int end);
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| /arch/x86/mm/pat/ |
| D | memtype_interval.c | 43 return entry->end - 1; in interval_end()
57 static struct memtype *memtype_match(u64 start, u64 end, int match_type) in memtype_match() argument
61 entry_match = interval_iter_first(&memtype_rbroot, start, end-1); in memtype_match()
63 while (entry_match != NULL && entry_match->start < end) { in memtype_match()
65 (entry_match->start == start) && (entry_match->end == end)) in memtype_match()
69 (entry_match->start < start) && (entry_match->end == end)) in memtype_match()
72 entry_match = interval_iter_next(entry_match, start, end-1); in memtype_match()
78 static int memtype_check_conflict(u64 start, u64 end, in memtype_check_conflict() argument
85 entry_match = interval_iter_first(&memtype_rbroot, start, end-1); in memtype_check_conflict()
92 dprintk("Overlap at 0x%Lx-0x%Lx\n", entry_match->start, entry_match->end); in memtype_check_conflict()
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| /arch/c6x/platforms/ |
| D | cache.c | 130 unsigned int *end, in cache_block_operation() argument
136 (L2_CACHE_ALIGN_CNT((unsigned int) end) in cache_block_operation()
175 unsigned int *end, in cache_block_operation_nowait() argument
181 (L2_CACHE_ALIGN_CNT((unsigned int) end) in cache_block_operation_nowait()
322 void enable_caching(unsigned long start, unsigned long end) in enable_caching() argument
325 unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2); in enable_caching()
331 void disable_caching(unsigned long start, unsigned long end) in disable_caching() argument
334 unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2); in disable_caching()
344 void L1P_cache_block_invalidate(unsigned int start, unsigned int end) in L1P_cache_block_invalidate() argument
347 (unsigned int *) end, in L1P_cache_block_invalidate()
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| /arch/arm/mm/ |
| D | cache-feroceon-l2.c | 73 static inline void l2_clean_pa_range(unsigned long start, unsigned long end) in l2_clean_pa_range() argument
82 BUG_ON((start ^ end) >> PAGE_SHIFT); in l2_clean_pa_range()
85 va_end = va_start + (end - start); in l2_clean_pa_range()
104 static inline void l2_inv_pa_range(unsigned long start, unsigned long end) in l2_inv_pa_range() argument
113 BUG_ON((start ^ end) >> PAGE_SHIFT); in l2_inv_pa_range()
116 va_end = va_start + (end - start); in l2_inv_pa_range()
142 static unsigned long calc_range_end(unsigned long start, unsigned long end) in calc_range_end() argument
147 BUG_ON(end & (CACHE_LINE_SIZE - 1)); in calc_range_end()
152 range_end = end; in calc_range_end()
171 static void feroceon_l2_inv_range(unsigned long start, unsigned long end) in feroceon_l2_inv_range() argument
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| /arch/s390/lib/ |
| D | delay.c | 38 u64 end; in __udelay_disabled() local
40 end = get_tod_clock() + (usecs << 12); in __udelay_disabled()
46 set_clock_comparator(end); in __udelay_disabled()
57 u64 clock_saved, end; in __udelay_enabled() local
59 end = get_tod_clock_fast() + (usecs << 12); in __udelay_enabled()
62 if (tod_after(S390_lowcore.clock_comparator, end)) { in __udelay_enabled()
64 set_clock_comparator(end); in __udelay_enabled()
69 } while (get_tod_clock_fast() < end); in __udelay_enabled()
111 u64 end; in udelay_simple() local
113 end = get_tod_clock_fast() + (usecs << 12); in udelay_simple()
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| /arch/arm/mach-pxa/ |
| D | devices.c | 42 .end = IRQ_PMU,
56 .end = 0x41100fff,
61 .end = IRQ_MMC,
97 .end = 0x4060ffff,
102 .end = IRQ_USB,
135 .end = 0x54100fff,
140 .end = IRQ_USB2,
161 .end = 0x4400ffff,
166 .end = IRQ_LCD,
193 .end = 0x40100023,
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| /arch/sh/mm/ |
| D | cache-sh2a.c | 53 unsigned long begin, end; in sh2a__flush_wback_region() local
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region()
66 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { in sh2a__flush_wback_region()
68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); in sh2a__flush_wback_region()
70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region()
78 for (v = begin; v < end; v += L1_CACHE_BYTES) in sh2a__flush_wback_region()
94 unsigned long begin, end; in sh2a__flush_purge_region() local
98 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_purge_region()
104 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh2a__flush_purge_region()
124 unsigned long begin, end; in sh2a__flush_invalidate_region() local
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| /arch/nds32/include/asm/ |
| D | proc-fns.h | 23 extern void cpu_dcache_inval_range(unsigned long start, unsigned long end);
24 extern void cpu_dcache_wb_range(unsigned long start, unsigned long end);
25 extern void cpu_dcache_wbinval_range(unsigned long start, unsigned long end);
29 extern void cpu_icache_inval_range(unsigned long start, unsigned long end);
33 unsigned long end, int flushi);
36 unsigned long end, bool flushi,
39 extern void cpu_dma_wb_range(unsigned long start, unsigned long end);
40 extern void cpu_dma_inval_range(unsigned long start, unsigned long end);
41 extern void cpu_dma_wbinval_range(unsigned long start, unsigned long end);
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| /arch/m68k/mm/ |
| D | cache.c | 79 unsigned long start, end; in flush_icache_user_range() local
81 end = endaddr & ICACHE_SET_MASK; in flush_icache_user_range()
82 if (start > end) { in flush_icache_user_range()
83 flush_cf_icache(0, end); in flush_icache_user_range()
84 end = ICACHE_MAX_ADDR; in flush_icache_user_range()
86 flush_cf_icache(start, end); in flush_icache_user_range()
122 unsigned long start, end; in flush_icache_user_page() local
124 end = (addr + len) & ICACHE_SET_MASK; in flush_icache_user_page()
125 if (start > end) { in flush_icache_user_page()
126 flush_cf_icache(0, end); in flush_icache_user_page()
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| /arch/x86/mm/ |
| D | numa_emulation.c | 32 static u64 __init mem_hole_size(u64 start, u64 end) in mem_hole_size() argument
35 unsigned long end_pfn = PFN_DOWN(end); in mem_hole_size()
60 eb->end = pb->start + size; in emu_setup_memblk()
67 if (pb->start >= pb->end) { in emu_setup_memblk()
68 WARN_ON_ONCE(pb->start > pb->end); in emu_setup_memblk()
73 nid, eb->start, eb->end - 1, (eb->end - eb->start) >> 20); in emu_setup_memblk()
129 u64 start, limit, end; in split_nodes_interleave() local
138 limit = pi->blk[phys_blk].end; in split_nodes_interleave()
139 end = start + size; in split_nodes_interleave()
142 end += FAKE_NODE_MIN_SIZE; in split_nodes_interleave()
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| D | kasan_init_64.c | 39 unsigned long end, int nid) in kasan_populate_pmd() argument
47 ((end - addr) == PMD_SIZE) && in kasan_populate_pmd()
71 } while (pte++, addr += PAGE_SIZE, addr != end); in kasan_populate_pmd()
75 unsigned long end, int nid) in kasan_populate_pud() argument
84 ((end - addr) == PUD_SIZE) && in kasan_populate_pud()
99 next = pmd_addr_end(addr, end); in kasan_populate_pud()
102 } while (pmd++, addr = next, addr != end); in kasan_populate_pud()
106 unsigned long end, int nid) in kasan_populate_p4d() argument
119 next = pud_addr_end(addr, end); in kasan_populate_p4d()
122 } while (pud++, addr = next, addr != end); in kasan_populate_p4d()
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| /arch/m68k/include/asm/ |
| D | cacheflush_mm.h | 31 static inline void clear_cf_icache(unsigned long start, unsigned long end) in clear_cf_icache() argument
40 static inline void clear_cf_dcache(unsigned long start, unsigned long end) in clear_cf_dcache() argument
49 static inline void clear_cf_bcache(unsigned long start, unsigned long end) in clear_cf_bcache() argument
62 static inline void flush_cf_icache(unsigned long start, unsigned long end) in flush_cf_icache() argument
66 for (set = start; set <= end; set += (0x10 - 3)) { in flush_cf_icache()
80 static inline void flush_cf_dcache(unsigned long start, unsigned long end) in flush_cf_dcache() argument
84 for (set = start; set <= end; set += (0x10 - 3)) { in flush_cf_dcache()
98 static inline void flush_cf_bcache(unsigned long start, unsigned long end) in flush_cf_bcache() argument
102 for (set = start; set <= end; set += (0x10 - 3)) { in flush_cf_bcache()
193 #define flush_cache_vmap(start, end) flush_cache_all() argument
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| /arch/s390/include/asm/ |
| D | mem_detect.h | 17 u64 end; member
38 void add_mem_detect_block(u64 start, u64 end);
41 unsigned long *end) in __get_mem_detect_block() argument
45 *end = 0; in __get_mem_detect_block()
51 *end = (unsigned long)mem_detect.entries[n].end; in __get_mem_detect_block()
54 *end = (unsigned long)mem_detect.entries_extended[n - MEM_INLINED_ENTRIES].end; in __get_mem_detect_block()
85 unsigned long end; in get_mem_detect_end() local
88 __get_mem_detect_block(mem_detect.count - 1, &start, &end); in get_mem_detect_end()
89 return end; in get_mem_detect_end()
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| /arch/s390/mm/ |
| D | vmem.c | 92 static void __vmemmap_use_sub_pmd(unsigned long start, unsigned long end) in __vmemmap_use_sub_pmd() argument
103 static void vmemmap_use_sub_pmd(unsigned long start, unsigned long end) in vmemmap_use_sub_pmd() argument
110 unused_pmd_start = end; in vmemmap_use_sub_pmd()
116 __vmemmap_use_sub_pmd(start, end); in vmemmap_use_sub_pmd()
119 static void vmemmap_use_new_sub_pmd(unsigned long start, unsigned long end) in vmemmap_use_new_sub_pmd() argument
126 __vmemmap_use_sub_pmd(start, end); in vmemmap_use_new_sub_pmd()
136 if (!IS_ALIGNED(end, PMD_SIZE)) in vmemmap_use_new_sub_pmd()
137 unused_pmd_start = end; in vmemmap_use_new_sub_pmd()
141 static bool vmemmap_unuse_sub_pmd(unsigned long start, unsigned long end) in vmemmap_unuse_sub_pmd() argument
146 memset(__va(start), PAGE_UNUSED, end - start); in vmemmap_unuse_sub_pmd()
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| /arch/mips/cavium-octeon/ |
| D | csrc-octeon.c | 146 u64 cur, end, inc; in __udelay() local
151 end = cur + inc; in __udelay()
153 while (end > cur) in __udelay()
160 u64 cur, end, inc; in __ndelay() local
165 end = cur + inc; in __ndelay()
167 while (end > cur) in __ndelay()
174 u64 cur, end; in __delay() local
177 end = cur + loops; in __delay()
179 while (end > cur) in __delay()
195 u64 cur, end; in octeon_io_clk_delay() local
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| /arch/arm/mach-davinci/ |
| D | devices-da8xx.c | 154 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
160 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
166 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
185 .end = DA850_TPCC1_BASE + SZ_32K - 1,
191 .end = DA850_TPTC2_BASE + SZ_1K - 1,
302 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
307 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
322 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
327 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
358 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
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| /arch/x86/kernel/ |
| D | resource.c | 6 resource_size_t end) in resource_clip() argument
10 if (res->end < start || res->start > end) in resource_clip()
16 if (res->end > end) in resource_clip()
17 high = res->end - end; in resource_clip()
21 res->end = start - 1; in resource_clip()
23 res->start = end + 1; in resource_clip()
|