Searched refs:errata (Results 1 – 25 of 26) sorted by relevance
12
82 unsigned errata = 0; in configure_dma_errata() local161 return errata; in configure_dma_errata()189 dma_plat_info.errata = configure_dma_errata(); in omap2_system_dma_init()
33 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
35 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
209 /* See 35xx errata 2.1.1.128 in SPRZ278F */
109 * AM335x errata for wiring:
250 /* default boot source: workaround #1 for errata ERR006282 */
476 * For more info, see errata advisory 2.1.87.
19 obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o
244 unsigned errata = 0; in configure_dma_errata() local253 return errata; in configure_dma_errata()372 p.errata = configure_dma_errata(); in omap1_system_dma_init()
156 @ work around errata of OMAP1510 PDE bit for TC shut down
840 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"849 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"858 bool "ARM errata: Stale prediction on replaced interworking branch"874 bool "ARM errata: Processor deadlock when a false hazard is created"888 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"901 bool "ARM errata: DMB operation may be faulty"914 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"929 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"940 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"952 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"[all …]
53 Enable workarounds for original MPC5200 errata. This is not required
314 bool "Enable linker work around for PPC476FPE errata #46"318 through pages (IBM errata #46). It requires a recent version326 # 44x errata/workaround config symbols, selected by the CPU models above
685 const char *errata[8]; in l2c310_fixup() local694 errata[n++] = "588369"; in l2c310_fixup()701 errata[n++] = "727915"; in l2c310_fixup()710 errata[n++] = "752271"; in l2c310_fixup()717 errata[n++] = "753970"; in l2c310_fixup()721 errata[n++] = "769419"; in l2c310_fixup()728 pr_cont(" %s", errata[i]); in l2c310_fixup()
1008 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"1020 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"1028 this errata (fixed in r3p1).1031 bool "PL310 errata: cache sync operation may be faulty"1045 bool "PL310 errata: no automatic Store Buffer drain"
108 teq r1, r2, lsr #4 @ test for errata affected core and if so...
69 static u32 errata; variable890 errata = p->errata; in omap_system_dma_probe()
42 bool "Enable A5 and A9 only errata work-arounds"
5 bool "Enable CN63XXP1 errata workarounds"
69 ERRATA Known errata for this release
109 .set UFLG_TMP,LV+121 | temporary for uflag errata
319 |** NOTE *** Bug fix for errata (0d43b #3)
363 menu "ARM errata workarounds via the alternatives framework"565 errata 1188873 and 1418040.777 Enable workaround for errata 22375 and 24313.779 This implements two gicv3-its errata workarounds for ThunderX. Both1882 Specific errata workaround(s) might also force module PLTs to be
2648 # R4600 erratum. Due to the lack of errata information the exact2655 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:2689 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
542 dmb @ errata #451034 on early Cortex A8