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Searched refs:gpc_base (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-imx/
Dgpc.c30 static void __iomem *gpc_base; variable
37 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); in imx_gpc_set_arm_power_up_timing()
43 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); in imx_gpc_set_arm_power_down_timing()
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
55 val = readl_relaxed(gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
59 writel_relaxed(val, gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
64 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_pre_suspend()
79 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_post_resume()
107 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_mask_all()
118 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; in imx_gpc_restore_all()
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Dpm-imx5.c135 static void __iomem *gpc_base; variable
154 arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()
156 empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()
158 empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
195 imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); in mx5_cpu_lp_set()
196 imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); in mx5_cpu_lp_set()
202 imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_cpu_lp_set()
203 imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_cpu_lp_set()
225 imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
226 imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
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Dpm-imx6.c226 struct imx6_pm_base gpc_base; member
542 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); in imx6q_suspend_init()
577 iounmap(pm_info->gpc_base.vbase); in imx6q_suspend_init()