| /arch/mips/loongson2ef/common/cs5536/ |
| D | cs5536_ehci.c | 17 u32 hi = 0, lo = value; in pci_ehci_write_reg() local
21 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); in pci_ehci_write_reg()
23 hi |= PCI_COMMAND_MASTER; in pci_ehci_write_reg()
25 hi &= ~PCI_COMMAND_MASTER; in pci_ehci_write_reg()
28 hi |= PCI_COMMAND_MEMORY; in pci_ehci_write_reg()
30 hi &= ~PCI_COMMAND_MEMORY; in pci_ehci_write_reg()
31 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); in pci_ehci_write_reg()
35 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ehci_write_reg()
38 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ehci_write_reg()
44 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_ehci_write_reg()
[all …]
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| D | cs5536_ide.c | 17 u32 hi = 0, lo = value; in pci_ide_write_reg() local
21 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); in pci_ide_write_reg()
26 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); in pci_ide_write_reg()
30 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ide_write_reg()
33 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ide_write_reg()
39 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
41 hi |= (value >> 8); in pci_ide_write_reg()
42 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); in pci_ide_write_reg()
46 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_ide_write_reg()
[all …]
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| D | cs5536_ohci.c | 17 u32 hi = 0, lo = value; in pci_ohci_write_reg() local
21 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); in pci_ohci_write_reg()
23 hi |= PCI_COMMAND_MASTER; in pci_ohci_write_reg()
25 hi &= ~PCI_COMMAND_MASTER; in pci_ohci_write_reg()
28 hi |= PCI_COMMAND_MEMORY; in pci_ohci_write_reg()
30 hi &= ~PCI_COMMAND_MEMORY; in pci_ohci_write_reg()
31 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); in pci_ohci_write_reg()
35 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_ohci_write_reg()
38 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_ohci_write_reg()
44 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_ohci_write_reg()
[all …]
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| D | cs5536_isa.c | 51 u32 hi, lo; in divil_lbar_enable() local
59 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_enable()
60 hi |= 0x01; in divil_lbar_enable()
61 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_enable()
70 u32 hi, lo; in divil_lbar_disable() local
74 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_disable()
75 hi &= ~0x01; in divil_lbar_disable()
76 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_disable()
86 u32 hi = 0, lo = value; in pci_isa_write_bar() local
89 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_isa_write_bar()
[all …]
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| D | cs5536_acc.c | 17 u32 hi = 0, lo = value; in pci_acc_write_reg() local
21 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); in pci_acc_write_reg()
26 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); in pci_acc_write_reg()
30 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); in pci_acc_write_reg()
33 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); in pci_acc_write_reg()
39 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); in pci_acc_write_reg()
41 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); in pci_acc_write_reg()
44 hi = 0xA0000000 | ((value & 0x000ff000) >> 12); in pci_acc_write_reg()
46 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo); in pci_acc_write_reg()
50 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); in pci_acc_write_reg()
[all …]
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| /arch/csky/kernel/ |
| D | perf_event.c | 92 uint32_t lo, hi, tmp; in csky_pmu_read_cc() local
98 hi = cprgr("<0, 0x3>"); in csky_pmu_read_cc()
99 } while (hi != tmp); in csky_pmu_read_cc()
101 result = (uint64_t) (hi) << 32; in csky_pmu_read_cc()
116 uint32_t lo, hi, tmp; in csky_pmu_read_ic() local
122 hi = cprgr("<0, 0x5>"); in csky_pmu_read_ic()
123 } while (hi != tmp); in csky_pmu_read_ic()
125 result = (uint64_t) (hi) << 32; in csky_pmu_read_ic()
140 uint32_t lo, hi, tmp; in csky_pmu_read_icac() local
146 hi = cprgr("<0, 0x7>"); in csky_pmu_read_icac()
[all …]
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| /arch/riscv/net/ |
| D | bpf_jit_comp32.c | 101 static s8 hi(const s8 *r) in hi() function
131 emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); in emit_imm32()
133 emit(rv_addi(hi(rd), RV_REG_ZERO, -1), ctx); in emit_imm32()
140 emit_imm(hi(rd), imm_hi, ctx); in emit_imm64()
151 emit(rv_addi(RV_REG_A1, hi(r0), 0), ctx); in __build_epilogue()
188 if (is_stacked(hi(reg))) { in bpf_get_reg64()
189 emit(rv_lw(hi(tmp), hi(reg), RV_REG_FP), ctx); in bpf_get_reg64()
199 if (is_stacked(hi(reg))) { in bpf_put_reg64()
200 emit(rv_sw(RV_REG_FP, hi(reg), hi(src)), ctx); in bpf_put_reg64()
221 emit(rv_sw(RV_REG_FP, hi(reg), RV_REG_ZERO), ctx); in bpf_put_reg32()
[all …]
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| /arch/sparc/kernel/ |
| D | trampoline_64.S | 85 sethi %hi(0x80000000), %g5
101 sethi %hi(0x80000000), %g2
108 sethi %hi(prom_entry_lock), %g2
116 sethi %hi(tramp_stack), %g1
129 sethi %hi(KERNBASE), %l3
130 sethi %hi(kern_locked_tte_data), %l4
133 sethi %hi(num_kernel_image_mappings), %l6
144 sethi %hi(call_method), %g2
151 sethi %hi(itlb_load), %g2
154 sethi %hi(prom_mmu_ihandle_cache), %g2
[all …]
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| D | sys32.S | 18 sethi %hi(sys_mmap), %g1
31 sethi %hi(__socketcall_table_begin), %g2
45 sethi %hi(sys_socket), %g1
54 sethi %hi(sys_bind), %g1
63 sethi %hi(sys_connect), %g1
72 sethi %hi(sys_listen), %g1
81 sethi %hi(sys_accept), %g1
90 sethi %hi(sys_getsockname), %g1
99 sethi %hi(sys_getpeername), %g1
108 sethi %hi(sys_socketpair), %g1
[all …]
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| /arch/sparc/mm/ |
| D | ultra.S | 42 sethi %hi(KERNBASE), %g3
74 sethi %hi(KERNBASE), %o4
106 sethi %hi(KERNBASE), %o4
124 sethi %hi(PAGE_SIZE), %o4
132 2: sethi %hi(KERNBASE), %o3
181 sethi %hi(KERNBASE), %o1
194 sethi %hi(PAGE_OFFSET), %g1
196 sethi %hi(PAGE_SIZE), %g2
219 sethi %hi(PAGE_OFFSET), %g1
223 sethi %hi(1 << 14), %o2 ! D-cache size
[all …]
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| D | viking.S | 39 sethi %hi(PAGE_OFFSET), %g2
44 sethi %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
45 sethi %hi(0x80000000), %o4
46 sethi %hi(VIKING_PTAG_VALID), %o5
47 sethi %hi(2*PAGE_SIZE), %o0
48 sethi %hi(PAGE_SIZE), %g7
92 sethi %hi(PAGE_OFFSET), %g2
95 sethi %hi(MXCC_SRCSTREAM), %o3 ! assume %hi(MXCC_SRCSTREAM) == %hi(MXCC_DESTSTREAM)
161 sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
206 sethi %hi(sun4dsmp_flush_tlb_spin), %g3
[all …]
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| /arch/arm/crypto/ |
| D | sha512-armv4.pl | 56 $hi="HI";
133 ldr $t3,[$Ktbl,#$hi] @ K[i].hi
294 ldr $Ehi,[$ctx,#$Eoff+$hi]
296 ldr $t1, [$ctx,#$Goff+$hi]
298 ldr $t3, [$ctx,#$Hoff+$hi]
305 ldr $Ahi,[$ctx,#$Aoff+$hi]
307 ldr $Thi,[$ctx,#$Boff+$hi]
309 ldr $t1, [$ctx,#$Coff+$hi]
311 ldr $t3, [$ctx,#$Doff+$hi]
319 ldr $Thi,[$ctx,#$Foff+$hi]
[all …]
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| /arch/x86/kernel/cpu/ |
| D | centaur.c | 24 u32 lo, hi; in init_c3() local
32 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
34 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
40 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
42 wrmsr(MSR_VIA_RNG, lo, hi); in init_c3()
54 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
56 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
120 u32 lo, hi, newlo; in init_centaur() local
184 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
190 wrmsr(MSR_IDT_FCR1, newlo, hi); in init_centaur()
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| D | zhaoxin.c | 22 u32 lo, hi; in init_zhaoxin_cap() local
30 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
33 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
39 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
42 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
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| /arch/sparc/lib/ |
| D | fls.S | 17 sethi %hi(0xffff0000), %g3
22 sethi %hi(0xff000000), %g3
25 sethi %hi(0xf0000000), %g3
32 sethi %hi(0xf0000000), %g3
36 sethi %hi(0xc0000000), %g3
58 sethi %hi(0xff000000), %g3
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| D | NG2patch.S | 10 sethi %hi(NEW), %g1; \
12 sethi %hi(OLD), %g2; \
15 sethi %hi(BRANCH_ALWAYS), %g3; \
21 sethi %hi(NOP), %g3; \
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| D | U3patch.S | 10 sethi %hi(NEW), %g1; \
12 sethi %hi(OLD), %g2; \
15 sethi %hi(BRANCH_ALWAYS), %g3; \
21 sethi %hi(NOP), %g3; \
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| D | GENpatch.S | 10 sethi %hi(NEW), %g1; \
12 sethi %hi(OLD), %g2; \
15 sethi %hi(BRANCH_ALWAYS), %g3; \
21 sethi %hi(NOP), %g3; \
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| D | NGpatch.S | 10 sethi %hi(NEW), %g1; \
12 sethi %hi(OLD), %g2; \
15 sethi %hi(BRANCH_ALWAYS), %g3; \
21 sethi %hi(NOP), %g3; \
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| D | clear_page.S | 44 sethi %hi(PAGE_OFFSET), %g2
45 sethi %hi(PAGE_SIZE), %o4
48 sethi %hi(PAGE_KERNEL_LOCKED), %g3
56 sethi %hi(TLBTEMP_BASE), %o3
70 sethi %hi(KERNBASE), %g1
80 sethi %hi(PAGE_SIZE/64), %o1
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| /arch/riscv/include/asm/ |
| D | timex.h | 73 u32 hi, lo; in get_cycles64() local
76 hi = get_cycles_hi(); in get_cycles64()
78 } while (hi != get_cycles_hi()); in get_cycles64()
80 return ((u64)hi << 32) | lo; in get_cycles64()
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| /arch/mips/loongson2ef/lemote-2f/ |
| D | reset.c | 44 u32 hi, lo; in fl2f_reboot() local
45 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); in fl2f_reboot()
47 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); in fl2f_reboot()
53 u32 hi, lo, val; in fl2f_shutdown() local
57 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); in fl2f_shutdown()
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| /arch/x86/kernel/cpu/mce/ |
| D | winchip.c | 31 u32 lo, hi; in winchip_mcheck_init() local
37 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
40 wrmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| /arch/m68k/ifpsp060/src/ |
| D | ilsp.S | 75 # 0x8(sp) = hi(dividend) #
138 mov.l 0xc(%a6), %d5 # get dividend hi
155 tst.l %d5 # chk sign of hi(dividend)
165 # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
167 tst.l %d5 # is (hi(dividend) == 0)
449 # returns 64 bit result in %d5 (hi) %d6(lo).
452 # multiply hi,lo words of each factor to get 4 intermediate products
528 # | hi(mplier) * hi(mplicand)| #
531 # | hi(mplier) * lo(mplicand) | #
534 # | lo(mplier) * hi(mplicand) | #
[all …]
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| /arch/x86/kernel/ |
| D | tsc_msr.c | 168 u32 lo, hi, ratio, freq, tscref; in cpu_khz_from_msr() local
181 rdmsr(MSR_PLATFORM_INFO, lo, hi); in cpu_khz_from_msr()
184 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in cpu_khz_from_msr()
185 ratio = (hi >> 8) & 0x1f; in cpu_khz_from_msr()
189 rdmsr(MSR_FSB_FREQ, lo, hi); in cpu_khz_from_msr()
|