| /arch/m68k/coldfire/ |
| D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
27 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
[all …]
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| /arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
[all …]
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| D | zynq-7000.dtsi | 48 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
106 interrupt-parent = <&intc>;
117 interrupt-parent = <&intc>;
129 interrupt-parent = <&intc>;
141 interrupt-parent = <&intc>;
150 interrupt-parent = <&intc>;
161 interrupt-parent = <&intc>;
168 intc: interrupt-controller@f8f01000 { label
213 interrupt-parent = <&intc>;
[all …]
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| D | mmp3.dtsi | 49 compatible = "marvell,mmp3-intc";
54 mrvl,intc-nr-irqs = <64>;
58 compatible = "mrvl,mmp2-mux-intc";
64 mrvl,intc-nr-irqs = <4>;
68 compatible = "mrvl,mmp2-mux-intc";
74 mrvl,intc-nr-irqs = <2>;
78 compatible = "mrvl,mmp2-mux-intc";
84 mrvl,intc-nr-irqs = <3>;
88 compatible = "mrvl,mmp2-mux-intc";
94 mrvl,intc-nr-irqs = <3>;
[all …]
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| D | vf500.dtsi | 28 intc: interrupt-controller@40003000 { label
32 interrupt-parent = <&intc>;
41 interrupt-parent = <&intc>;
59 interrupt-parent = <&intc>;
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| D | mmp2.dtsi | 27 interrupt-parent = <&intc>;
53 intc: interrupt-controller@d4282000 { label
54 compatible = "mrvl,mmp2-intc";
58 mrvl,intc-nr-irqs = <64>;
62 compatible = "mrvl,mmp2-mux-intc";
68 mrvl,intc-nr-irqs = <2>;
72 compatible = "mrvl,mmp2-mux-intc";
78 mrvl,intc-nr-irqs = <2>;
83 compatible = "mrvl,mmp2-mux-intc";
89 mrvl,intc-nr-irqs = <3>;
[all …]
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| /arch/arm/mach-s3c/ |
| D | irq-s3c24xx.c | 47 struct s3c_irq_intc *intc; member
81 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask() local
82 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
87 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
89 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
109 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask() local
110 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
114 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
116 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
128 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_ack() local
[all …]
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| /arch/mips/boot/dts/ingenic/ |
| D | x1000.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
81 interrupt-parent = <&intc>;
97 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
[all …]
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| D | x1830.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
81 interrupt-parent = <&intc>;
97 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
[all …]
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| D | jz4770.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4770-intc";
92 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
155 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
185 interrupt-parent = <&intc>;
200 interrupt-parent = <&intc>;
215 interrupt-parent = <&intc>;
230 interrupt-parent = <&intc>;
[all …]
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| D | jz4740.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
111 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
181 interrupt-parent = <&intc>;
192 interrupt-parent = <&intc>;
222 interrupt-parent = <&intc>;
[all …]
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| D | jz4780.dtsi | 41 intc: interrupt-controller@10001000 { label
42 compatible = "ingenic,jz4780-intc";
92 interrupt-parent = <&intc>;
132 interrupt-parent = <&intc>;
157 interrupt-parent = <&intc>;
172 interrupt-parent = <&intc>;
187 interrupt-parent = <&intc>;
202 interrupt-parent = <&intc>;
217 interrupt-parent = <&intc>;
232 interrupt-parent = <&intc>;
[all …]
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| D | jz4725b.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
120 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
190 interrupt-parent = <&intc>;
207 interrupt-parent = <&intc>;
231 interrupt-parent = <&intc>;
[all …]
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| /arch/mips/boot/dts/ralink/ |
| D | rt3050.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
|
| D | mt7620a.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
|
| D | rt3883.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
|
| D | rt2880.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
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| D | mt7628a.dtsi | 144 interrupt-parent = <&intc>;
150 intc: interrupt-controller@200 { label
151 compatible = "ralink,rt2880-intc";
158 reset-names = "intc";
163 ralink,intc-registers = <0x9c 0xa0
182 interrupt-parent = <&intc>;
228 interrupt-parent = <&intc>;
244 interrupt-parent = <&intc>;
260 interrupt-parent = <&intc>;
285 interrupt-parent = <&intc>;
|
| /arch/arc/boot/dts/ |
| D | vdk_axc003_idu.dtsi | 8 * HS38x2 (Dual Core) with IDU intc (VDK version)
31 core_intc: archs-intc@cpu {
32 compatible = "snps,archs-intc";
38 compatible = "snps,archs-idu-intc";
|
| D | axc003_idu.dtsi | 7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
45 core_intc: archs-intc@cpu {
46 compatible = "snps,archs-intc";
52 compatible = "snps,archs-idu-intc";
60 * to uplink only 1 IRQ to ARC core intc
134 * This intc actually resides on MB, but we move it here to
136 * this intc to cpu intc are different for axs101 and axs103
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| D | axc003.dtsi | 45 core_intc: archs-intc@cpu {
46 compatible = "snps,archs-intc";
53 * to uplink only 1 IRQ to ARC core intc
120 * The DW APB ICTL intc on MB is connected to CPU intc via a
128 * This intc actually resides on MB, but we move it here to
130 * this intc to cpu intc are different for axs101 and axs103
|
| D | axc001.dtsi | 37 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc700-intc";
45 * to uplink only 1 IRQ to ARC core intc
90 * This intc actually resides on MB, but we move it here to
92 * this intc to cpu intc are different for axs101 and axs103
|