| /arch/xtensa/include/asm/ |
| D | bitops.h | 101 #define BIT_OP(op, insn, inv) \ argument
116 : [mask] "a" (inv mask), [addr] "a" (p) \
120 #define TEST_AND_BIT_OP(op, insn, inv) \ argument
136 : [mask] "a" (inv mask), [addr] "a" (p) \
144 #define BIT_OP(op, insn, inv) \ argument
160 : [mask] "a" (inv mask) \
164 #define TEST_AND_BIT_OP(op, insn, inv) \ argument
181 : [mask] "a" (inv mask) \
189 #define BIT_OP(op, insn, inv) argument
190 #define TEST_AND_BIT_OP(op, insn, inv) argument
[all …]
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| /arch/arm/mm/ |
| D | proc-feroceon.S | 252 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
253 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
298 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
299 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
361 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
362 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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| /arch/mips/boot/dts/brcm/ |
| D | bcm63268-comtrend-vr-3032u.dts | 25 brcm,serial-shift-inv;
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| /arch/x86/events/zhaoxin/ |
| D | core.c | 440 PMU_FORMAT_ATTR(inv, "config:23");
570 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
573 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
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| /arch/x86/events/intel/ |
| D | p6.c | 188 PMU_FORMAT_ATTR(inv, "config:23" );
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| D | knc.c | 278 PMU_FORMAT_ATTR(inv, "config:23" );
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| D | core.c | 3436 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3464 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
3488 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3960 PMU_FORMAT_ATTR(inv, "config:23" );
5073 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5076 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5231 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5234 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5271 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5274 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
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| D | uncore_snb.c | 136 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| D | uncore_nhmex.c | 194 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| D | uncore_snbep.c | 462 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| /arch/x86/events/amd/ |
| D | core.c | 718 PMU_FORMAT_ATTR(inv, "config:23" );
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| /arch/x86/events/ |
| D | perf_event.h | 611 inv:1, member
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| D | core.c | 1877 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); in x86_event_sysfs_show() local
1898 if (inv) in x86_event_sysfs_show()
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| /arch/arm/crypto/ |
| D | aes-neonbs-core.S | 297 t0, t1, t2, t3, t4, t5, t6, t7, inv argument
336 .ifb \inv
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| /arch/arm64/crypto/ |
| D | aes-neonbs-core.S | 250 t0, t1, t2, t3, t4, t5, t6, t7, inv argument
289 .ifb \inv
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| /arch/arm/boot/dts/ |
| D | omap3-n900.dts | 840 clock-inv = <0>;
|