| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 25 mfspr r3,SPRN_HID4
32 mfspr r3,SPRN_HID5
40 mfspr r0,SPRN_HID1
76 mfspr r0,SPRN_HID0
90 mfspr r0,SPRN_HID0
98 mfspr r0,SPRN_HID0
99 mfspr r0,SPRN_HID0
100 mfspr r0,SPRN_HID0
101 mfspr r0,SPRN_HID0
102 mfspr r0,SPRN_HID0
[all …]
|
| D | head_44x.S | 314 mfspr r10, SPRN_DEAR /* Get faulting address */
325 mfspr r12,SPRN_MMUCR
332 mfspr r11,SPRN_SPRG_THREAD
336 mfspr r12,SPRN_MMUCR
337 mfspr r13,SPRN_PID /* Get PID */
356 mfspr r12,SPRN_ESR
394 mfspr r10,SPRN_DEAR
403 mfspr r11, SPRN_SPRG_RSCRATCH4
405 mfspr r13, SPRN_SPRG_RSCRATCH3
406 mfspr r12, SPRN_SPRG_RSCRATCH2
[all …]
|
| D | head_40x.S | 108 mfspr r11,SPRN_SRR3; /* check whether user or kernel */\
115 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
124 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
126 mfspr r9,SPRN_ESR; /* in them at the point where the */\
128 mfspr r12,SPRN_SRR2; \
130 mfspr r9,SPRN_SRR3; \
183 mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */
185 mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
206 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
214 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
[all …]
|
| D | cpu_setup_power.c | 64 fscr = mfspr(SPRN_FSCR); in init_FSCR()
73 fscr = mfspr(SPRN_FSCR); in init_FSCR_power9()
83 fscr = mfspr(SPRN_FSCR); in init_FSCR_power10()
93 hfscr = mfspr(SPRN_HFSCR); in init_HFSCR()
141 init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH); in __setup_cpu_power7()
154 init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH); in __restore_cpu_power7()
168 init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */ in __setup_cpu_power8()
188 init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */ in __restore_cpu_power8()
206 init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\ in __setup_cpu_power9()
227 init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\ in __restore_cpu_power9()
[all …]
|
| D | fsl_booke_entry_mapping.S | 8 mfspr r7, SPRN_PID0
13 mfspr r7,SPRN_MAS1
17 mfspr r7,SPRN_MMUCFG
22 mfspr r7,SPRN_PID1
27 mfspr r7,SPRN_MAS1
30 mfspr r7, SPRN_PID2
37 mfspr r7,SPRN_MAS0
40 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
46 mfspr r9,SPRN_TLB1CFG
53 mfspr r7,SPRN_MAS1
[all …]
|
| D | cpu_setup_fsl_booke.S | 20 mfspr r0, SPRN_L1CSR1
30 mfspr r0, SPRN_L1CSR0
42 1: mfspr r0, SPRN_L1CSR0
59 mfspr r3, SPRN_PWRMGTCR0
78 mfspr r3, SPRN_PWRMGTCR0
97 mfspr r10,SPRN_MMUCFG
114 mfspr r3,SPRN_HID0
130 mfspr r3,SPRN_HID1
148 mfspr r3, SPRN_MMUCFG
176 mfspr r10,SPRN_MMUCFG
[all …]
|
| D | head_booke.h | 49 mfspr r10, SPRN_SPRG_THREAD; \
53 mfspr r11, SPRN_SRR1; \
66 mfspr r13, SPRN_SPRG_RSCRATCH0; \
73 mfspr r12,SPRN_SRR0; \
75 mfspr r9,SPRN_SRR1; \
87 mfspr r10, SPRN_SPRG_THREAD
94 mfspr r11, SPRN_SRR1
107 mfspr r9, SPRN_SRR1
117 mfspr r12,SPRN_SRR0
211 mfspr r8,SPRN_PIR; \
[all …]
|
| D | swsusp_booke.S | 65 mfspr r4,SPRN_TCR
69 1: mfspr r4,SPRN_TBRU
71 mfspr r5,SPRN_TBRL
73 mfspr r3,SPRN_TBRU
78 mfspr r4,SPRN_SPRG0
80 mfspr r4,SPRN_SPRG1
82 mfspr r4,SPRN_SPRG2
84 mfspr r4,SPRN_SPRG3
86 mfspr r4,SPRN_SPRG4
88 mfspr r4,SPRN_SPRG5
[all …]
|
| D | cpu_setup_6xx.S | 85 mfspr r11,SPRN_HID0
103 mfspr r11,SPRN_HID0
140 mfspr r11,SPRN_MSSSR0
162 mfspr r11,SPRN_HID0
186 mfspr r10, SPRN_HID1
221 mfspr r11,SPRN_L3CR
232 mfspr r11,SPRN_HID0
263 mfspr r3,SPRN_L2CR
266 mfspr r3,SPRN_MSSCR0
327 mfspr r3,SPRN_HID0
[all …]
|
| D | head_32.h | 23 mfspr r10, SPRN_SPRG_THREAD
25 mfspr r11, SPRN_DAR
27 mfspr r11, SPRN_DSISR
30 mfspr r11, SPRN_SRR0
33 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
46 mfspr r1,SPRN_SPRG_THREAD
52 mfspr r11,SPRN_SPRG_THREAD
73 mfspr r10, SPRN_SPRG_SCRATCH0
90 mfspr r12,SPRN_SPRG_SCRATCH1
95 mfspr r12, SPRN_SPRG_THREAD
[all …]
|
| D | l2cr_6xx.S | 116 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
123 mfspr r4,SPRN_L2CR
154 mfspr r4,SPRN_MSSCR0
217 10: mfspr r3,SPRN_L2CR
224 3: mfspr r3,SPRN_L2CR
244 mfspr r3,SPRN_MSSCR0
269 mfspr r3,SPRN_L2CR
299 mfspr r4,SPRN_L3CR
350 10: mfspr r3,SPRN_L3CR
388 mfspr r3,SPRN_L3CR
[all …]
|
| D | head_8xx.S | 210 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
217 mfspr r10, SPRN_M_TWB /* Get level 1 table */
227 mfspr r10, SPRN_MD_TWC
244 0: mfspr r10, SPRN_SPRG_SCRATCH0
245 mfspr r11, SPRN_SPRG_SCRATCH1
254 mfspr r10, SPRN_SPRG_SCRATCH0
255 mfspr r11, SPRN_SPRG_SCRATCH1
268 mfspr r10, SPRN_MD_EPN
270 mfspr r10, SPRN_M_TWB /* Get level 1 table */
279 mfspr r10, SPRN_MD_TWC
[all …]
|
| D | head_fsl_booke.S | 215 mfspr r24,SPRN_PIR
376 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
378 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
439 mfspr r10, SPRN_SPRG_THREAD
443 mfspr r11, SPRN_SRR1
452 mfspr r11, SPRN_SRR1
458 mfspr r10, SPRN_DEAR /* Get faulting address */
469 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
477 mfspr r11,SPRN_SPRG_THREAD
494 mfspr r12,SPRN_ESR
[all …]
|
| /arch/powerpc/kvm/ |
| D | book3s_hv_interrupts.S | 46 mfspr r3, SPRN_DSCR
51 mfspr r3, SPRN_DABR
71 mfspr r8,SPRN_DEC
117 mfspr r8, SPRN_MMCR2
123 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
125 mfspr r6, SPRN_MMCRA
133 mfspr r5, SPRN_MMCR1
134 mfspr r9, SPRN_SIAR
135 mfspr r10, SPRN_SDAR
142 mfspr r9, SPRN_SIER
[all …]
|
| D | bookehv_interrupts.S | 71 mfspr r10, SPRN_PID
82 1: mfspr r7, SPRN_TBRU
83 mfspr r8, SPRN_TBRL
84 mfspr r9, SPRN_TBRU
146 mfspr r8, SPRN_ESR
151 mfspr r9, SPRN_DEAR
188 mfspr r12, \scratch
190 mfspr r5, \scratch
202 mfspr r5, \srr0
203 mfspr r6, \srr1
[all …]
|
| D | e500mc.c | 76 val = mfspr(SPRN_MAS1); in kvmppc_e500_tlbil_one()
142 if (vcpu->arch.oldpir != mfspr(SPRN_PIR) || in kvmppc_core_vcpu_load_e500mc()
151 vcpu->arch.eplc = mfspr(SPRN_EPLC); in kvmppc_core_vcpu_put_e500mc()
152 vcpu->arch.epsc = mfspr(SPRN_EPSC); in kvmppc_core_vcpu_put_e500mc()
154 vcpu->arch.shared->sprg0 = mfspr(SPRN_GSPRG0); in kvmppc_core_vcpu_put_e500mc()
155 vcpu->arch.shared->sprg1 = mfspr(SPRN_GSPRG1); in kvmppc_core_vcpu_put_e500mc()
156 vcpu->arch.shared->sprg2 = mfspr(SPRN_GSPRG2); in kvmppc_core_vcpu_put_e500mc()
157 vcpu->arch.shared->sprg3 = mfspr(SPRN_GSPRG3); in kvmppc_core_vcpu_put_e500mc()
159 vcpu->arch.shared->srr0 = mfspr(SPRN_GSRR0); in kvmppc_core_vcpu_put_e500mc()
160 vcpu->arch.shared->srr1 = mfspr(SPRN_GSRR1); in kvmppc_core_vcpu_put_e500mc()
[all …]
|
| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 69 mfspr r5, SPRN_HID0
70 mfspr r6, SPRN_HID1
71 mfspr r7, SPRN_HID2
77 mfspr r4, SPRN_IABR
78 mfspr r5, SPRN_IABR2
79 mfspr r6, SPRN_IBCR
80 mfspr r7, SPRN_DABR
81 mfspr r8, SPRN_DABR2
82 mfspr r9, SPRN_DBCR
91 mfspr r4, SPRN_SPRG0
[all …]
|
| /arch/powerpc/include/asm/ |
| D | oprofile_impl.h | 71 return mfspr(SPRN_PMC1); in classic_ctr_read()
73 return mfspr(SPRN_PMC2); in classic_ctr_read()
75 return mfspr(SPRN_PMC3); in classic_ctr_read()
77 return mfspr(SPRN_PMC4); in classic_ctr_read()
79 return mfspr(SPRN_PMC5); in classic_ctr_read()
81 return mfspr(SPRN_PMC6); in classic_ctr_read()
86 return mfspr(SPRN_PMC7); in classic_ctr_read()
88 return mfspr(SPRN_PMC8); in classic_ctr_read()
|
| D | idle.h | 14 *this_cpu_ptr(&idle_entry_purr_snap) = mfspr(SPRN_PURR); in snapshot_purr_idle_entry()
19 *this_cpu_ptr(&idle_entry_spurr_snap) = mfspr(SPRN_SPURR); in snapshot_spurr_idle_entry()
28 wait_cycles += mfspr(SPRN_PURR) - in_purr; in update_idle_purr_accounting()
37 *idle_spurr_cycles_ptr += mfspr(SPRN_SPURR) - in_spurr; in update_idle_spurr_accounting()
|
| /arch/powerpc/oprofile/ |
| D | op_model_pa6t.c | 33 return mfspr(SPRN_PA6T_PMC0); in ctr_read()
35 return mfspr(SPRN_PA6T_PMC1); in ctr_read()
37 return mfspr(SPRN_PA6T_PMC2); in ctr_read()
39 return mfspr(SPRN_PA6T_PMC3); in ctr_read()
41 return mfspr(SPRN_PA6T_PMC4); in ctr_read()
43 return mfspr(SPRN_PA6T_PMC5); in ctr_read()
143 mfspr(SPRN_PA6T_MMCR0)); in pa6t_cpu_setup()
145 mfspr(SPRN_PA6T_MMCR1)); in pa6t_cpu_setup()
177 mmcr0 = mfspr(SPRN_PA6T_MMCR0); in pa6t_stop()
190 unsigned long pc = mfspr(SPRN_PA6T_SIAR); in pa6t_handle_interrupt()
[all …]
|
| /arch/openrisc/kernel/ |
| D | setup.c | 98 unsigned long upr = mfspr(SPR_UPR); in print_cpuinfo()
99 unsigned long vr = mfspr(SPR_VR); in print_cpuinfo()
133 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), in print_cpuinfo()
134 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); in print_cpuinfo()
137 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), in print_cpuinfo()
138 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); in print_cpuinfo()
182 iccfgr = mfspr(SPR_ICCFGR); in setup_cpuinfo()
189 dccfgr = mfspr(SPR_DCCFGR); in setup_cpuinfo()
204 cpuinfo->coreid = mfspr(SPR_COREID); in setup_cpuinfo()
331 vr = mfspr(SPR_VR); in show_cpuinfo()
[all …]
|
| /arch/powerpc/platforms/powernv/ |
| D | idle.c | 74 uint64_t lpcr_val = mfspr(SPRN_LPCR); in pnv_save_sprs_for_deep_states()
75 uint64_t hid0_val = mfspr(SPRN_HID0); in pnv_save_sprs_for_deep_states()
76 uint64_t hmeer_val = mfspr(SPRN_HMEER); in pnv_save_sprs_for_deep_states()
117 uint64_t hid1_val = mfspr(SPRN_HID1); in pnv_save_sprs_for_deep_states()
118 uint64_t hid4_val = mfspr(SPRN_HID4); in pnv_save_sprs_for_deep_states()
119 uint64_t hid5_val = mfspr(SPRN_HID5); in pnv_save_sprs_for_deep_states()
341 sprs.tscr = mfspr(SPRN_TSCR); in power7_idle_insn()
342 sprs.worc = mfspr(SPRN_WORC); in power7_idle_insn()
344 sprs.sdr1 = mfspr(SPRN_SDR1); in power7_idle_insn()
345 sprs.rpr = mfspr(SPRN_RPR); in power7_idle_insn()
[all …]
|
| D | subcore-asm.S | 43 mfspr r6, SPRN_LDBAR
44 mfspr r7, SPRN_PMMAR
45 mfspr r8, SPRN_PMCR
46 mfspr r9, SPRN_RPR
47 mfspr r10, SPRN_SDR1
60 1: mfspr r4, SPRN_HID0
|
| /arch/powerpc/platforms/powermac/ |
| D | cache.S | 56 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
85 mfspr r3,SPRN_HID0
99 mfspr r5,SPRN_L2CR
156 1: mfspr r3,SPRN_L2CR
167 mfspr r0,SPRN_HID0
175 mfspr r0,SPRN_HID0
204 mfspr r0,SPRN_MSSCR0
246 mfspr r6,SPRN_LDSTCR
271 mfspr r3,SPRN_L2CR
291 3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
[all …]
|
| D | sleep.S | 136 mfspr r4,SPRN_DBAT4U
138 mfspr r4,SPRN_DBAT4L
140 mfspr r4,SPRN_DBAT5U
142 mfspr r4,SPRN_DBAT5L
144 mfspr r4,SPRN_DBAT6U
146 mfspr r4,SPRN_DBAT6L
148 mfspr r4,SPRN_DBAT7U
150 mfspr r4,SPRN_DBAT7L
152 mfspr r4,SPRN_IBAT4U
154 mfspr r4,SPRN_IBAT4L
[all …]
|