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Searched refs:mis (Results 1 – 6 of 6) sorted by relevance

/arch/x86/events/intel/
Dlbr.c841 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; in intel_pmu_lbr_read_64() local
860 mis = !!(info & LBR_INFO_MISPRED); in intel_pmu_lbr_read_64()
861 pred = !mis; in intel_pmu_lbr_read_64()
868 mis = !!(from & LBR_FROM_FLAG_MISPRED); in intel_pmu_lbr_read_64()
869 pred = !mis; in intel_pmu_lbr_read_64()
877 mis = !!(from & LBR_FROM_FLAG_MISPRED); in intel_pmu_lbr_read_64()
878 pred = !mis; in intel_pmu_lbr_read_64()
901 cpuc->lbr_entries[out].mispred = mis; in intel_pmu_lbr_read_64()
/arch/arm/boot/dts/
Dspear310.dtsi108 st-plgpio,mis-reg = <0x60>;
Dspear320.dtsi136 st-plgpio,mis-reg = <0x84>;
Dspear1340.dtsi164 st-plgpio,mis-reg = <0xa0>;
Dspear1310.dtsi308 st-plgpio,mis-reg = <0x10>;
/arch/arm64/
DKconfig653 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"