| /arch/arm64/kvm/vgic/ |
| D | vgic-irqfd.c | 55 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
56 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
57 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
58 e->msi.flags = ue->flags; in kvm_set_routing_entry()
59 e->msi.devid = ue->u.msi.devid; in kvm_set_routing_entry()
70 struct kvm_msi *msi) in kvm_populate_msi() argument
72 msi->address_lo = e->msi.address_lo; in kvm_populate_msi()
73 msi->address_hi = e->msi.address_hi; in kvm_populate_msi()
74 msi->data = e->msi.data; in kvm_populate_msi()
75 msi->flags = e->msi.flags; in kvm_populate_msi()
[all …]
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| D | vgic-v4.c | 371 struct kvm_msi msi = (struct kvm_msi) { in vgic_get_its() local
372 .address_lo = irq_entry->msi.address_lo, in vgic_get_its()
373 .address_hi = irq_entry->msi.address_hi, in vgic_get_its()
374 .data = irq_entry->msi.data, in vgic_get_its()
375 .flags = irq_entry->msi.flags, in vgic_get_its()
376 .devid = irq_entry->msi.devid, in vgic_get_its()
379 return vgic_msi_to_its(kvm, &msi); in vgic_get_its()
404 ret = vgic_its_resolve_lpi(kvm, its, irq_entry->msi.devid, in kvm_vgic_v4_set_forwarding()
405 irq_entry->msi.data, &irq); in kvm_vgic_v4_set_forwarding()
458 ret = vgic_its_resolve_lpi(kvm, its, irq_entry->msi.devid, in kvm_vgic_v4_unset_forwarding()
[all …]
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| /arch/powerpc/platforms/4xx/ |
| D | msi.c | 128 struct resource res, struct ppc4xx_msi *msi) in ppc4xx_setup_pcieh_hw() argument
149 msi->msi_dev = of_find_node_by_name(NULL, "ppc4xx-msi"); in ppc4xx_setup_pcieh_hw()
150 if (!msi->msi_dev) in ppc4xx_setup_pcieh_hw()
153 msi->msi_regs = of_iomap(msi->msi_dev, 0); in ppc4xx_setup_pcieh_hw()
154 if (!msi->msi_regs) { in ppc4xx_setup_pcieh_hw()
160 (u32) (msi->msi_regs + PEIH_TERMADH), (u32) (msi->msi_regs)); in ppc4xx_setup_pcieh_hw()
167 msi->msi_addr_hi = upper_32_bits(msi_phys); in ppc4xx_setup_pcieh_hw()
168 msi->msi_addr_lo = lower_32_bits(msi_phys & 0xffffffff); in ppc4xx_setup_pcieh_hw()
170 msi->msi_addr_hi, msi->msi_addr_lo); in ppc4xx_setup_pcieh_hw()
176 out_be32(msi->msi_regs + PEIH_TERMADH, msi->msi_addr_hi); in ppc4xx_setup_pcieh_hw()
[all …]
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| /arch/powerpc/sysdev/ |
| D | fsl_msi.c | 35 #define msi_hwirq(msi, msir_index, intr_index) \ argument
36 ((msir_index) << (msi)->srs_shift | \
37 ((intr_index) << (msi)->ibs_shift))
328 struct fsl_msi *msi = platform_get_drvdata(ofdev); in fsl_of_msi_remove() local
331 if (msi->list.prev != NULL) in fsl_of_msi_remove()
332 list_del(&msi->list); in fsl_of_msi_remove()
334 if (msi->cascade_array[i]) { in fsl_of_msi_remove()
335 virq = msi->cascade_array[i]->virq; in fsl_of_msi_remove()
339 free_irq(virq, msi->cascade_array[i]); in fsl_of_msi_remove()
340 kfree(msi->cascade_array[i]); in fsl_of_msi_remove()
[all …]
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| D | Makefile | 5 mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o
6 obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
10 obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
12 fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
21 obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
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| /arch/mips/boot/dts/loongson/ |
| D | loongson64c_4core_ls7a.dts | 28 msi: msi-controller@2ff00000 { label
29 compatible = "loongson,pch-msi-1.0";
32 msi-controller;
33 loongson,msi-base-vec = <64>;
34 loongson,msi-num-vecs = <64>;
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| D | loongson64g_4core_ls7a.dts | 32 msi: msi-controller@2ff00000 { label
33 compatible = "loongson,pch-msi-1.0";
36 msi-controller;
37 loongson,msi-base-vec = <64>;
38 loongson,msi-num-vecs = <192>;
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| /arch/s390/pci/ |
| D | pci_irq.c | 240 struct msi_desc *msi; in arch_setup_msi_irqs() local
276 for_each_pci_msi_entry(msi, pdev) { in arch_setup_msi_irqs()
282 msi->affinity : NULL); in arch_setup_msi_irqs()
285 rc = irq_set_msi_desc(irq, msi); in arch_setup_msi_irqs()
292 if (msi->affinity) in arch_setup_msi_irqs()
293 cpu = cpumask_first(&msi->affinity->mask); in arch_setup_msi_irqs()
329 struct msi_desc *msi; in arch_teardown_msi_irqs() local
341 for_each_pci_msi_entry(msi, pdev) { in arch_teardown_msi_irqs()
342 if (!msi->irq) in arch_teardown_msi_irqs()
344 if (msi->msi_attrib.is_msix) in arch_teardown_msi_irqs()
[all …]
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| /arch/x86/kvm/ |
| D | irq_comm.c | 107 trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ? in kvm_set_msi_irq()
108 (u64)e->msi.address_hi << 32 : 0), in kvm_set_msi_irq()
109 e->msi.data); in kvm_set_msi_irq()
111 irq->dest_id = (e->msi.address_lo & in kvm_set_msi_irq()
114 irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi); in kvm_set_msi_irq()
115 irq->vector = (e->msi.data & in kvm_set_msi_irq()
118 !!((1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo)); in kvm_set_msi_irq()
119 irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data; in kvm_set_msi_irq()
120 irq->delivery_mode = e->msi.data & 0x700; in kvm_set_msi_irq()
121 irq->msi_redir_hint = ((e->msi.address_lo in kvm_set_msi_irq()
[all …]
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| /arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-post.dtsi | 75 msi@41600 {
76 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
78 msi@41800 {
79 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
81 msi@41a00 {
82 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
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| D | qoriq-mpic.dtsi | 54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
57 msi-available-ranges = <0 0x100>;
69 msi1: msi@41800 {
70 compatible = "fsl,mpic-msi";
72 msi-available-ranges = <0 0x100>;
84 msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi";
87 msi-available-ranges = <0 0x100>;
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| D | qoriq-mpic4.3.dtsi | 54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi-v4.3";
76 msi1: msi@41800 {
77 compatible = "fsl,mpic-msi-v4.3";
98 msi2: msi@41a00 {
99 compatible = "fsl,mpic-msi-v4.3";
120 msi3: msi@41c00 {
121 compatible = "fsl,mpic-msi-v4.3";
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| D | mpc8572ds_camp_core1.dts | 7 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
87 0xe0 0xe1 0xe2 0xe3 /* msi */
93 msi@41600 {
94 msi-available-ranges = <0x80 0x80>;
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| D | mpc8572ds_camp_core0.dts | 59 0xe4 0xe5 0xe6 0xe7 /* msi */
63 msi@41600 {
64 msi-available-ranges = <0 0x80>;
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| /arch/arm64/boot/dts/marvell/ |
| D | armada-ap80x.dtsi | 92 msi-controller;
94 arm,msi-base-spi = <160>;
95 arm,msi-num-spis = <32>;
99 msi-controller;
101 arm,msi-base-spi = <192>;
102 arm,msi-num-spis = <32>;
106 msi-controller;
108 arm,msi-base-spi = <224>;
109 arm,msi-num-spis = <32>;
113 msi-controller;
[all …]
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| D | armada-ap810-ap0.dtsi | 59 msi-controller;
60 #msi-cells = <1>;
77 msi-parent = <&gic_its_ap0 0xa0>;
85 msi-parent = <&gic_its_ap0 0xa1>;
93 msi-parent = <&gic_its_ap0 0xa2>;
101 msi-parent = <&gic_its_ap0 0xa3>;
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| /arch/arm64/boot/dts/arm/ |
| D | foundation-v8-gicv3.dtsi | 22 its: msi-controller@2f020000 {
24 msi-controller;
25 #msi-cells = <1>;
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| /arch/arm64/boot/dts/broadcom/northstar2/ |
| D | ns2.dtsi | 142 msi-parent = <&v2m0>;
173 msi-parent = <&v2m0>;
191 msi-parent = <&v2m0>;
373 msi-controller;
375 arm,msi-base-spi = <72>;
376 arm,msi-num-spis = <16>;
382 msi-controller;
384 arm,msi-base-spi = <88>;
385 arm,msi-num-spis = <16>;
391 msi-controller;
[all …]
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| /arch/sparc/kernel/ |
| D | pci_fire.c | 158 unsigned long *head, unsigned long *msi) in pci_fire_dequeue_msi() argument
176 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >> in pci_fire_dequeue_msi()
200 unsigned long msi, int is_msi64) in pci_fire_msi_setup()
204 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
207 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
209 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi)); in pci_fire_msi_setup()
211 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
213 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
218 static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) in pci_fire_msi_teardown() argument
222 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_teardown()
[all …]
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| D | pci_msi.c | 30 unsigned long msi; in sparc64_msiq_interrupt() local
32 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
36 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
129 int msi, err; in sparc64_setup_msi_irq() local
144 msi = err; in sparc64_setup_msi_irq()
148 err = ops->msi_setup(pbm, msiqid, msi, in sparc64_setup_msi_irq()
153 pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p; in sparc64_setup_msi_irq()
162 msg.data = msi; in sparc64_setup_msi_irq()
170 free_msi(pbm, msi); in sparc64_setup_msi_irq()
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| /arch/powerpc/platforms/cell/ |
| D | axon_msi.c | 96 u32 write_offset, msi; in axon_msi_cascade() local
108 msi = le32_to_cpu(msic->fifo_virt[idx]); in axon_msi_cascade()
109 msi &= 0xFFFF; in axon_msi_cascade()
112 write_offset, msic->read_offset, msi); in axon_msi_cascade()
114 if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { in axon_msi_cascade()
115 generic_handle_irq(msi); in axon_msi_cascade()
126 pr_devel("axon_msi: invalid irq 0x%x!\n", msi); in axon_msi_cascade()
132 msi, retry); in axon_msi_cascade()
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| /arch/arm64/boot/dts/hisilicon/ |
| D | hip07.dtsi | 929 msi-controller;
930 #msi-cells = <1>;
936 msi-controller;
937 #msi-cells = <1>;
943 msi-controller;
944 #msi-cells = <1>;
950 msi-controller;
951 #msi-cells = <1>;
957 msi-controller;
958 #msi-cells = <1>;
[all …]
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| D | hip05.dtsi | 247 msi-controller;
248 #msi-cells = <1>;
254 msi-controller;
255 #msi-cells = <1>;
261 msi-controller;
262 #msi-cells = <1>;
268 msi-controller;
269 #msi-cells = <1>;
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| /arch/arm/boot/dts/ |
| D | bcm-nsp.dtsi | 553 msi-parent = <&msi0>;
554 msi0: msi-controller {
555 compatible = "brcm,iproc-msi";
556 msi-controller;
562 brcm,pcie-msi-inten;
590 msi-parent = <&msi1>;
591 msi1: msi-controller {
592 compatible = "brcm,iproc-msi";
593 msi-controller;
599 brcm,pcie-msi-inten;
[all …]
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| D | bcm-hr2.dtsi | 320 msi-parent = <&msi0>;
321 msi0: msi-controller {
322 compatible = "brcm,iproc-msi";
323 msi-controller;
329 brcm,pcie-msi-inten;
356 msi-parent = <&msi1>;
357 msi1: msi-controller {
358 compatible = "brcm,iproc-msi";
359 msi-controller;
365 brcm,pcie-msi-inten;
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