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Searched refs:r23 (Results 1 – 25 of 95) sorted by relevance

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/arch/parisc/kernel/
Dpacache.S540 sub %r25, %r1, %r23
548 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
555 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
953 ldw R%dcache_stride(%r1), %r23
961 sub %r25, %r23, %r25
963 1: fdc,m %r23(%r26)
964 fdc,m %r23(%r26)
965 fdc,m %r23(%r26)
966 fdc,m %r23(%r26)
967 fdc,m %r23(%r26)
[all …]
Dsys_parisc32.c19 asmlinkage long sys32_unimplemented(int r26, int r25, int r24, int r23, in sys32_unimplemented() argument
/arch/ia64/lib/
Dflush.S36 shr.u r23=in0,r20 // start / (stride size)
40 sub r8=r22,r23 // number of strides - 1
41 shl r24=r23,r20 // r24: addresses for "fc.i" =
90 shr.u r23=in0,r20 // start / (stride size)
94 sub r8=r22,r23 // number of strides - 1
95 shl r24=r23,r20 // r24: addresses for "fc" =
Dip_fast_csum.S49 ld4 r23=[r15],8
53 add r22=r22,r23
105 ld4 r23=[in1],4
112 add r17=r22,r23
/arch/sh/boot/compressed/
Dhead_64.S96 movi ICCR1_INIT_VAL, r23
98 putcfg r21, ICCR_REG1, r23
104 movi OCCR1_INIT_VAL, r23
106 putcfg r21, OCCR_REG1, r23
130 movi datalabel _end, r23
133 bne r22, r23, tr1
/arch/powerpc/kexec/
Drelocate_32.S98 tlbsx r23,0,r5 /* Find entry we are in */
101 1: cmpw r23,r4 /* Is this our entry? */
111 andi. r6, r23, 1 /* Find the index to use */
119 tlbre r3, r23, PPC44x_TLB_PAGEID
120 tlbre r4, r23, PPC44x_TLB_XLAT
121 tlbre r5, r23, PPC44x_TLB_ATTRIB
173 tlbwe r3, r23, PPC44x_TLB_PAGEID
244 2: mflr r23
245 tlbsx r23, 0, r23
246 tlbre r24, r23, 0 /* TLB Word 0 */
[all …]
/arch/parisc/include/asm/
Dunistd.h83 #define K_LOAD_ARGS_4(r26,r25,r24,r23) \ argument
84 register unsigned long __r23 __asm__("r23") = (unsigned long)(r23); \
86 #define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \ argument
88 K_LOAD_ARGS_4(r26,r25,r24,r23)
89 #define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \ argument
91 K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
Dasmregs.h12 arg3: .reg %r23
56 r23: .reg %r23
/arch/powerpc/kernel/
Dhead_44x.S866 tlbsx r23,0,r5 /* Find entry we are in */
869 1: cmpw r23,r4 /* Is this our entry? */
888 tlbre r25,r23,PPC44x_TLB_XLAT
943 3: cmpwi r23,63
946 tlbwe r6,r23,PPC44x_TLB_PAGEID
1057 1: mflr r23
1058 tlbsx r23,0,r23
1059 tlbre r24,r23,0
1060 tlbre r25,r23,1
1061 tlbre r26,r23,2
[all …]
Didle_book3s.S70 std r23,-8*11(r1)
115 ld r23,-8*11(r1)
178 std r23,-8*11(r1)
Dmisc.S66 PPC_STL r23,14*SZL(r3)
94 PPC_LL r23,14*SZL(r3)
Dhead_64.S425 LOAD_REG_ADDR(r23, cur_cpu_spec)
426 ld r23,0(r23)
427 ld r12,CPU_SPEC_RESTORE(r23)
444 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
446 cmpwi 0,r23,0
/arch/microblaze/lib/
Duaccess_old.S112 6: lwi r23, r6, 0x0014 + offset; \
120 14: swi r23, r5, 0x0014 + offset; \
200 swi r23, r1, 28
223 lwi r23, r1, 28
243 lwi r23, r1, 28
/arch/ia64/kernel/
Dfsys.S222 add r23 = IA64_CLKSRC_SHIFT_OFFSET,r20
231 ld4 r23 = [r23] // clocksource shift value
271 shr.u r8 = r8,r23 // shift by factor
278 add r23 = IA64_TIMESPEC_TV_NSEC_OFFSET, r31
295 EX(.fail_efault, probe.w.fault r23, 3) // This also costs 5 cycles
304 EX(.fail_efault, st8 [r23] = r21)
487 MOV_FROM_ITC(p0, p6, r30, r23) // M get cycle for accounting
493 mov r23=ar.bspstore // M2 (12 cyc) save ar.bspstore
Divt.S186 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
202 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
353 THASH(p8, r17, r16, r23)
355 MOV_TO_IHA(p8, r17, r23)
359 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
364 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
408 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
415 cmp.ne p8,p0=r0,r23
741 mov.m r23=ar.bspstore // M2 (12 cyc)
871 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
[all …]
/arch/csky/abiv2/
Dmemcpy.S45 ldw r23, (r1, 12)
49 stw r23, (r0, 12)
Dmemmove.S51 ldw r23, (r1, 12)
55 stw r23, (r0, 12)
/arch/arc/include/asm/
Dunwind.h37 unsigned long r23; member
96 PTREGS_INFO(r23), \
/arch/alpha/include/uapi/asm/
Dptrace.h34 unsigned long r23; member
/arch/arc/include/uapi/asm/
Dptrace.h45 unsigned long r25, r24, r23, r22, r21, r20; member
/arch/hexagon/include/uapi/asm/
Duser.h37 unsigned long r23; member
/arch/hexagon/include/asm/
Dprocessor.h108 unsigned long r23; member
/arch/powerpc/crypto/
Daes-spe-regs.h29 #define rW7 r23
/arch/nios2/include/asm/
Dptrace.h60 unsigned long r23; member
/arch/powerpc/boot/
Dppc_asm.h48 #define r23 23 macro

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