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Searched refs:reg1 (Results 1 – 25 of 42) sorted by relevance

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/arch/nios2/include/asm/
Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
[all …]
/arch/arm64/include/asm/
Dkvm_ptrauth.h26 .macro ptrauth_save_state base, reg1, reg2
27 mrs_s \reg1, SYS_APIAKEYLO_EL1
29 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)]
30 mrs_s \reg1, SYS_APIBKEYLO_EL1
32 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)]
33 mrs_s \reg1, SYS_APDAKEYLO_EL1
35 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)]
36 mrs_s \reg1, SYS_APDBKEYLO_EL1
38 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)]
39 mrs_s \reg1, SYS_APGAKEYLO_EL1
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Dasm-uaccess.h66 .macro uao_ldp l, reg1, reg2, addr, post_inc
67 8888: ldtr \reg1, [\addr];
75 .macro uao_stp l, reg1, reg2, addr, post_inc
76 8888: sttr \reg1, [\addr];
/arch/s390/include/asm/
Dap.h57 register unsigned long reg1 asm ("1") = 0; in ap_instructions_available()
65 : "+d" (reg1), "+d" (reg2) in ap_instructions_available()
68 return reg1 != 0; in ap_instructions_available()
81 register struct ap_queue_status reg1 asm ("1"); in ap_tapq()
85 : "=d" (reg1), "=d" (reg2) in ap_tapq()
90 return reg1; in ap_tapq()
119 register struct ap_queue_status reg1 asm ("1"); in ap_rapq()
123 : "=d" (reg1) in ap_rapq()
126 return reg1; in ap_rapq()
138 register struct ap_queue_status reg1 asm ("1"); in ap_zapq()
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Dsigp.h44 register unsigned long reg1 asm ("1") = parm; in ____pcpu_sigp()
51 : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); in ____pcpu_sigp()
52 *status = reg1; in ____pcpu_sigp()
Dtimex.h111 register unsigned long reg1 asm("1") = (unsigned long) (ptff_block);\
118 : "=d" (rc), "+m" (*(struct addrtype *) reg1) \
119 : "d" (reg0), "d" (reg1) : "cc"); \
/arch/arm/probes/kprobes/
Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/arch/arm/lib/
Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
45 .macro enter reg1 reg2
46 stmdb sp!, {r0, \reg1, \reg2}
49 .macro usave reg1 reg2
50 UNWIND( .save {r0, \reg1, \reg2} )
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Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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Dcsumpartialcopyuser.S38 .macro load1b, reg1 argument
39 ldrusr \reg1, r0, 1
42 .macro load2b, reg1, reg2
43 ldrusr \reg1, r0, 1
47 .macro load1l, reg1 argument
48 ldrusr \reg1, r0, 4
51 .macro load2l, reg1, reg2
52 ldrusr \reg1, r0, 4
56 .macro load4l, reg1, reg2, reg3, reg4
57 ldrusr \reg1, r0, 4
Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
93 .macro enter reg1 reg2
95 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
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/arch/arm/kernel/
Dhyp-stub.S29 .macro store_primary_cpu_mode reg1, reg2, reg3
30 mrs \reg1, cpsr
31 and \reg1, \reg1, #MODE_MASK
34 str \reg1, [\reg2, \reg3]
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
46 ldr \reg1, [\reg2, \reg3]
47 cmp \mode, \reg1 @ matches primary CPU boot mode?
48 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
49 strne \reg1, [\reg2, \reg3] @ record what happened and give up
54 .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
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/arch/x86/events/intel/
Duncore_nhmex.c353 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config() local
368 reg1->reg = NHMEX_B0_MSR_MATCH; in nhmex_bbox_hw_config()
370 reg1->reg = NHMEX_B1_MSR_MATCH; in nhmex_bbox_hw_config()
371 reg1->idx = 0; in nhmex_bbox_hw_config()
372 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
380 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_msr_enable_event() local
383 if (reg1->idx != EXTRA_REG_NONE) { in nhmex_bbox_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
444 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_sbox_hw_config() local
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Duncore_snbep.c618 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in snbep_uncore_msr_enable_event() local
620 if (reg1->idx != EXTRA_REG_NONE) in snbep_uncore_msr_enable_event()
621 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); in snbep_uncore_msr_enable_event()
909 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; in snbep_cbox_put_constraint() local
917 if (reg1->alloc & (0x1 << i)) in snbep_cbox_put_constraint()
920 reg1->alloc = 0; in snbep_cbox_put_constraint()
927 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; in __snbep_cbox_get_constraint() local
933 if (reg1->idx == EXTRA_REG_NONE) in __snbep_cbox_get_constraint()
938 if (!(reg1->idx & (0x1 << i))) in __snbep_cbox_get_constraint()
940 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) in __snbep_cbox_get_constraint()
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/arch/arm64/crypto/
Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
23 ubfiz \reg1, \in1e, #2, #8
26 ubfx \reg1, \in1e, #\shift, #8
38 ldr \reg1, [tt, \reg1, uxtw #2]
42 lsl \reg1, \reg1, #2
45 ldrb \reg1, [tt, \reg1, uxtw]
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
51 ubfx \reg1, \in1d, #\shift, #8
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
/arch/arm64/lib/
Dmemcpy.S51 .macro ldp1 reg1, reg2, ptr, val
52 ldp \reg1, \reg2, [\ptr], \val
55 .macro stp1 reg1, reg2, ptr, val
56 stp \reg1, \reg2, [\ptr], \val
Dcopy_to_user.S46 .macro ldp1 reg1, reg2, ptr, val
47 ldp \reg1, \reg2, [\ptr], \val
50 .macro stp1 reg1, reg2, ptr, val
51 uao_stp 9997f, \reg1, \reg2, \ptr, \val
Dcopy_from_user.S47 .macro ldp1 reg1, reg2, ptr, val
48 uao_ldp 9997f, \reg1, \reg2, \ptr, \val
51 .macro stp1 reg1, reg2, ptr, val
52 stp \reg1, \reg2, [\ptr], \val
Dcopy_in_user.S48 .macro ldp1 reg1, reg2, ptr, val
49 uao_ldp 9997f, \reg1, \reg2, \ptr, \val
52 .macro stp1 reg1, reg2, ptr, val
53 uao_stp 9997f, \reg1, \reg2, \ptr, \val
/arch/s390/kvm/
Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
Dpriv.c262 int reg1, reg2; in handle_iske() local
275 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_iske()
301 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
302 vcpu->run->s.regs.gprs[reg1] |= key; in handle_iske()
309 int reg1, reg2; in handle_rrbe() local
322 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_rrbe()
360 int reg1, reg2; in handle_sske() local
380 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sske()
382 key = vcpu->run->s.regs.gprs[reg1] & 0xfe; in handle_sske()
426 vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; in handle_sske()
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/arch/s390/boot/
Dmem_detect.c72 unsigned long reg1, reg2; in __diag260() local
86 : "=&d" (reg1), "=&a" (reg2), in __diag260()
118 unsigned long reg1, reg2; in tprot() local
133 : [reg1] "=&d" (reg1), in tprot()
/arch/x86/crypto/
Dcrct10dif-pcl-asm_64.S64 # Fold reg1, reg2 into the next 32 data bytes, storing the result back into
65 # reg1, reg2.
66 .macro fold_32_bytes offset, reg1, reg2
71 movdqa \reg1, %xmm8
73 pclmulqdq $0x00, FOLD_CONSTS, \reg1
77 pxor %xmm9 , \reg1
78 xorps %xmm8 , \reg1
/arch/arm/crypto/
Dcrct10dif-ce-core.S117 .macro fold_32_bytes, reg1, reg2
120 vmull.p64 q8, \reg1\()h, FOLD_CONST_H
121 vmull.p64 \reg1, \reg1\()l, FOLD_CONST_L
130 veor.8 \reg1, \reg1, q8
132 veor.8 \reg1, \reg1, q11

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