/arch/riscv/kernel/ |
D | mcount.S | 18 sd s0, 0(sp) 20 addi s0, sp, 16 29 sd s0, 16(sp) 32 addi s0, sp, 32 37 ld s0, 0(sp) 43 ld s0, 16(sp) 67 mv t6, s0 104 addi a0, s0, -8 107 ld a2, -16(s0) 120 ld a1, -8(s0)
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D | mcount-dyn.S | 19 sd s0, 32(sp) 21 addi s0, sp, 48 29 sd s0, 0(sp) 31 addi s0, sp, 16 37 ld s0, 32(sp) 42 ld s0, 0(sp) 57 sd s0, 0(sp) 59 addi s0, sp, 16 68 ld s0, 0(sp) 79 ld a1, -8(s0) [all …]
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D | entry.S | 75 REG_L s0, TASK_TI_USER_SP(tp) 81 REG_S s0, PT_SP(sp) 193 la s0, sys_ni_syscall 200 la s0, sys_call_table 202 add s0, s0, t0 203 REG_L s0, 0(s0) 205 jalr s0 222 REG_L s0, PT_STATUS(sp) 230 and s0, s0, t0 232 andi s0, s0, SR_SPP [all …]
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/arch/arm/crypto/ |
D | sha2-ce-core.S | 32 .macro add_only, ev, s0 argument 34 .ifnb \s0 39 .ifnb \s0 40 vadd.u32 ta\ev, q\s0, k\ev 44 .macro add_update, ev, s0, s1, s2, s3 45 sha256su0.32 q\s0, q\s1 47 sha256su1.32 q\s0, q\s2, q\s3
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D | sha1-ce-core.S | 36 .macro add_only, op, ev, rc, s0, dg1 37 .ifnb \s0 38 vadd.u32 tb\ev, q\s0, \rc 48 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 49 sha1su0.32 q\s0, q\s1, q\s2 51 sha1su1.32 q\s0, q\s3
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D | sha512-armv4.pl | 559 my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps 569 vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1] 572 vshr.u64 $t0,$s0,#@sigma0[0] 574 vshr.u64 $t1,$s0,#@sigma0[1] 576 vshr.u64 $s1,$s0,#@sigma0[2] 577 vsli.64 $t0,$s0,#`64-@sigma0[0]` 578 vsli.64 $t1,$s0,#`64-@sigma0[1]` 579 vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9] 582 vadd.i64 @X[$i%8],$s0
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D | aes-neonbs-core.S | 193 t0, t1, t2, t3, s0, s1, s2, s3 198 veor \s0, \x0, \x2 201 vand \s2, \t3, \s0 202 vorr \t3, \t3, \s0 203 veor \s0, \s0, \t1 206 vand \s3, \s3, \s0 209 veor \s0, \x1, \x0 212 vand \s1, \t1, \s0 213 vorr \t1, \t1, \s0 219 vand \s0, \x7, \x3 [all …]
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D | blake2s-core.S | 68 .macro _blake2s_quarterround a0, b0, c0, d0, a1, b1, c1, d1, s0, s1, s2, s3 70 ldr M_0, [sp, #32 + 4 * \s0] 128 .macro _blake2s_round s0, s1, s2, s3, s4, s5, s6, s7, \ 135 \s0, \s1, \s2, \s3
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/arch/mips/kernel/ |
D | relocate_kernel.S | 20 PTR_L s0, kexec_indirection_page 24 PTR_L s2, (s0) 25 PTR_ADDIU s0, s0, SZREG 43 and s0, s2, ~0x2 125 1: LONG_L s0, (t0) 126 bne s0, zero,1b
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D | entry.S | 36 LONG_S s0, TI_REGS($28) 74 jal s0
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/arch/arm64/crypto/ |
D | sm3-ce-core.S | 43 .macro round, ab, s0, t0, t1, i 48 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i 51 .macro qround, ab, s0, s1, s2, s3, s4 54 ext v6.16b, \s0\().16b, \s1\().16b, #12 56 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s 59 eor v10.16b, \s0\().16b, \s1\().16b 61 round \ab, \s0, v11, v12, 0 62 round \ab, \s0, v12, v11, 1 63 round \ab, \s0, v11, v12, 2 64 round \ab, \s0, v12, v11, 3
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D | sha2-ce-core.S | 29 .macro add_only, ev, rc, s0 argument 32 add t1.4s, v\s0\().4s, \rc\().4s 36 .ifnb \s0 37 add t0.4s, v\s0\().4s, \rc\().4s 44 .macro add_update, ev, rc, s0, s1, s2, s3 45 sha256su0 v\s0\().4s, v\s1\().4s 47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
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D | sha1-ce-core.S | 34 .macro add_only, op, ev, rc, s0, dg1 36 add t1.4s, v\s0\().4s, \rc\().4s 44 .ifnb \s0 45 add t0.4s, v\s0\().4s, \rc\().4s 52 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s 55 sha1su1 v\s0\().4s, v\s3\().4s
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D | aes-neonbs-core.S | 138 t0, t1, t2, t3, s0, s1, s2, s3 143 eor \s0, \x0, \x2 146 and \s2, \t3, \s0 147 orr \t3, \t3, \s0 148 eor \s0, \s0, \t1 151 and \s3, \s3, \s0 154 eor \s0, \x1, \x0 157 and \s1, \t1, \s0 158 orr \t1, \t1, \s0 164 and \s0, \x7, \x3 [all …]
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/arch/riscv/include/asm/ |
D | ptrace.h | 23 unsigned long s0; member 91 return regs->s0; in frame_pointer() 96 regs->s0 = val; in frame_pointer_set()
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/arch/mips/boot/compressed/ |
D | head.S | 23 move s0, a0 43 move a0, s0
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/arch/mips/alchemy/devboards/ |
D | db1000.c | 446 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; in db1000_dev_setup() local 455 s0 = AU1500_GPIO1_INT; in db1000_dev_setup() 462 s0 = AU1100_GPIO1_INT; in db1000_dev_setup() 498 s0 = AU1000_GPIO1_INT; in db1000_dev_setup() 504 s0 = AU1500_GPIO202_INT; in db1000_dev_setup() 517 s0 = AU1100_GPIO10_INT; in db1000_dev_setup() 534 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); in db1000_dev_setup()
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/arch/mips/include/asm/ |
D | regdef.h | 42 #define s0 $16 /* callee saved */ macro 85 #define s0 $16 /* callee saved */ macro
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D | asmmacro-64.h | 18 LONG_S s0, THREAD_REG16(\thread) 31 LONG_L s0, THREAD_REG16(\thread)
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D | asmmacro-32.h | 65 LONG_S s0, THREAD_REG16(\thread) 78 LONG_L s0, THREAD_REG16(\thread)
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/arch/mips/power/ |
D | hibernate_asm.S | 20 PTR_S s0, PT_R16(t0) 50 PTR_L s0, PT_R16(t0)
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/arch/x86/crypto/ |
D | twofish-x86_64-asm_64-3way.S | 14 #define s0 0 macro 144 g1g2_3(ab, cd, s0, s1, s2, s3, s0, s1, s2, s3, RX, RY); \ 151 g1g2_3(ba, dc, s1, s2, s3, s0, s3, s0, s1, s2, RY, RX); \
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/arch/alpha/include/uapi/asm/ |
D | regdef.h | 16 #define s0 $9 /* saved-registers (callee-saved registers) */ macro
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/arch/mips/fw/lib/ |
D | call_o32.S | 56 REG_S s0,O32_FRAMESZ-11*SZREG(sp) 90 REG_L s0,O32_FRAMESZ-11*SZREG(sp)
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/arch/riscv/include/uapi/asm/ |
D | ptrace.h | 28 unsigned long s0; member
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