| /arch/mips/sgi-ip22/ |
| D | ip22-mc.c | 60 unsigned int tmp = get_bank_config(i); in probe_memory() local
61 if (!(tmp & SGIMC_MCONFIG_BVALID)) in probe_memory()
64 size = get_bank_size(tmp); in probe_memory()
65 addr = get_bank_addr(tmp); in probe_memory()
77 u32 tmp; in sgimc_init() local
94 tmp = sgimc->cpuctrl0; in sgimc_init()
95 tmp &= ~SGIMC_CCTRL0_WDOG; in sgimc_init()
96 sgimc->cpuctrl0 = tmp; in sgimc_init()
109 tmp = sgimc->cpuctrl0; in sgimc_init()
111 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; in sgimc_init()
[all …]
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| /arch/csky/kernel/probes/ |
| D | simulate-insn.c | 125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16() local
127 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
135 unsigned long tmp = opcode & 0x1f; in simulate_jmp32() local
137 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp32()
139 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp32()
145 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jsr16() local
147 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr16()
151 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr16()
157 unsigned long tmp = opcode & 0x1f; in simulate_jsr32() local
[all …]
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| /arch/arm/mach-zx/ |
| D | zx296702-pm-domain.c | 42 u32 tmp; in normal_power_off() local
44 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); in normal_power_off()
45 tmp &= ~BIT(zpd->bit); in normal_power_off()
46 writel_relaxed(tmp, pcubase + PCU_DM_CLKEN); in normal_power_off()
49 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); in normal_power_off()
50 tmp &= ~BIT(zpd->bit); in normal_power_off()
51 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN); in normal_power_off()
54 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); in normal_power_off()
55 tmp &= ~BIT(zpd->bit); in normal_power_off()
56 writel_relaxed(tmp, pcubase + PCU_DM_RSTEN); in normal_power_off()
[all …]
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| /arch/csky/include/asm/ |
| D | spinlock.h | 19 u32 tmp; in arch_spin_lock() local
27 : "=&r" (tmp), "=&r" (lockval) in arch_spin_lock()
39 u32 tmp, contended, res; in arch_spin_trylock() local
54 : "=&r" (res), "=&r" (tmp), "=&r" (contended) in arch_spin_trylock()
102 u32 tmp; in arch_spin_lock() local
110 : "=&r" (tmp) in arch_spin_lock()
125 u32 tmp; in arch_spin_trylock() local
135 : "=&r" (tmp) in arch_spin_trylock()
139 if (!tmp) in arch_spin_trylock()
142 return !tmp; in arch_spin_trylock()
[all …]
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| /arch/arm/mm/ |
| D | abort-macro.S | 13 .macro do_thumb_abort, fsr, pc, psr, tmp argument
16 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
18 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
19 cmp \tmp, # 0x5600 @ Is it ldrsb?
20 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
21 tst \tmp, #1 << 11 @ L = 0 -> write
34 .macro teq_ldrd, tmp, insn
35 mov \tmp, #0x0e100000
36 orr \tmp, #0x000000f0
37 and \tmp, \insn, \tmp
[all …]
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| D | proc-v7-3level.S | 117 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp argument
118 ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
119 cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
120 mov \tmp, #TTB_EAE @ for TTB control egister
121 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
122 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
123 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
124 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
130 orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
131 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
[all …]
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| /arch/sh/include/asm/ |
| D | spinlock-llsc.h | 28 unsigned long tmp; in arch_spin_lock() local
40 : "=&z" (tmp), "=&r" (oldval) in arch_spin_lock()
48 unsigned long tmp; in arch_spin_unlock() local
55 : "=&z" (tmp) in arch_spin_unlock()
63 unsigned long tmp, oldval; in arch_spin_trylock() local
73 : "=&z" (tmp), "=&r" (oldval) in arch_spin_trylock()
92 unsigned long tmp; in arch_read_lock() local
102 : "=&z" (tmp) in arch_read_lock()
110 unsigned long tmp; in arch_read_unlock() local
118 : "=&z" (tmp) in arch_read_unlock()
[all …]
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| D | bitops-grb.h | 9 unsigned long tmp; in set_bit() local
23 : "=&r" (tmp), in set_bit()
33 unsigned long tmp; in clear_bit() local
46 : "=&r" (tmp), in clear_bit()
56 unsigned long tmp; in change_bit() local
69 : "=&r" (tmp), in change_bit()
79 unsigned long tmp; in test_and_set_bit() local
97 : "=&r" (tmp), in test_and_set_bit()
110 unsigned long tmp; in test_and_clear_bit() local
130 : "=&r" (tmp), in test_and_clear_bit()
[all …]
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| D | bitops-llsc.h | 9 unsigned long tmp; in set_bit() local
20 : "=&z" (tmp) in set_bit()
30 unsigned long tmp; in clear_bit() local
41 : "=&z" (tmp) in clear_bit()
51 unsigned long tmp; in change_bit() local
62 : "=&z" (tmp) in change_bit()
72 unsigned long tmp; in test_and_set_bit() local
85 : "=&z" (tmp), "=&r" (retval) in test_and_set_bit()
97 unsigned long tmp; in test_and_clear_bit() local
111 : "=&z" (tmp), "=&r" (retval) in test_and_clear_bit()
[all …]
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-spinlock.h | 105 unsigned int tmp; in cvmx_spinlock_trylock() local
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp) in cvmx_spinlock_trylock()
120 return tmp != 0; /* normalize to 0 or 1 */ in cvmx_spinlock_trylock()
130 unsigned int tmp; in cvmx_spinlock_lock() local
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp) in cvmx_spinlock_lock()
163 unsigned int tmp; in cvmx_spinlock_bit_lock() local
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) in cvmx_spinlock_bit_lock()
195 unsigned int tmp; in cvmx_spinlock_bit_trylock() local
210 [val] "+m"(*word), [tmp] "=&r"(tmp) in cvmx_spinlock_bit_trylock()
213 return tmp != 0; /* normalize to 0 or 1 */ in cvmx_spinlock_bit_trylock()
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| /arch/xtensa/include/asm/ |
| D | tlbflush.h | 66 unsigned long tmp; in itlb_probe() local
67 __asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); in itlb_probe()
68 return tmp; in itlb_probe()
73 unsigned long tmp; in dtlb_probe() local
74 __asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); in dtlb_probe()
75 return tmp; in dtlb_probe()
125 unsigned long tmp; in read_ptevaddr_register() local
126 __asm__ __volatile__("rsr %0, ptevaddr\n\t" : "=a" (tmp)); in read_ptevaddr_register()
127 return tmp; in read_ptevaddr_register()
178 unsigned long tmp; in read_dtlb_virtual() local
[all …]
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| D | atomic.h | 61 unsigned long tmp; \
70 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
79 unsigned long tmp; \
89 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
100 unsigned long tmp; \
109 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
114 return tmp; \
121 unsigned long tmp; \
130 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
140 unsigned long tmp; \
[all …]
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| /arch/arm/include/asm/ |
| D | uaccess-asm.h | 19 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
21 adds \tmp, \addr, #\size - 1
22 sbcscc \tmp, \tmp, \limit
31 .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
33 sub \tmp, \limit, #1
34 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
35 addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
36 subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
37 movlo \addr, #0 @ if (tmp < 0) addr = NULL
42 .macro uaccess_disable, tmp, isb=1
[all …]
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| D | vfpmacros.h | 31 .macro VFPFLDMIA, base, tmp
41 ldr \tmp, =elf_hwcap @ may not have MVFR regs
42 ldr \tmp, [\tmp, #0]
43 tst \tmp, #HWCAP_VFPD32
47 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
48 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
49 cmp \tmp, #2 @ 32 x 64bit registers?
57 .macro VFPFSTMIA, base, tmp
66 ldr \tmp, =elf_hwcap @ may not have MVFR regs
67 ldr \tmp, [\tmp, #0]
[all …]
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| /arch/s390/lib/ |
| D | find.c | 21 unsigned long tmp; in find_first_bit_inv() local
24 if ((tmp = *(p++))) in find_first_bit_inv()
31 tmp = (*p) & (~0UL << (BITS_PER_LONG - size)); in find_first_bit_inv()
32 if (!tmp) /* Are any bits set? */ in find_first_bit_inv()
35 return result + (__fls(tmp) ^ (BITS_PER_LONG - 1)); in find_first_bit_inv()
44 unsigned long tmp; in find_next_bit_inv() local
51 tmp = *(p++); in find_next_bit_inv()
52 tmp &= (~0UL >> offset); in find_next_bit_inv()
55 if (tmp) in find_next_bit_inv()
61 if ((tmp = *(p++))) in find_next_bit_inv()
[all …]
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| /arch/alpha/math-emu/ |
| D | qrnnd.S | 41 #define tmp $3 macro
52 $loop1: cmplt n0,0,tmp
54 bis n1,tmp,n1
57 subq n1,d,tmp
58 cmovne qb,tmp,n1
60 cmplt n0,0,tmp
62 bis n1,tmp,n1
65 subq n1,d,tmp
66 cmovne qb,tmp,n1
68 cmplt n0,0,tmp
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| /arch/mips/bcm63xx/ |
| D | cpu.c | 129 unsigned int tmp, mips_pll_fcvo; in detect_cpu_clock() local
131 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); in detect_cpu_clock()
132 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) in detect_cpu_clock()
164 unsigned int tmp, n1, n2, m1; in detect_cpu_clock() local
167 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); in detect_cpu_clock()
168 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; in detect_cpu_clock()
169 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; in detect_cpu_clock()
170 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; in detect_cpu_clock()
179 unsigned int tmp, n1, n2, m1; in detect_cpu_clock() local
182 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); in detect_cpu_clock()
[all …]
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| /arch/sparc/include/asm/ |
| D | backoff.h | 55 #define BACKOFF_SPIN(reg, tmp, label) \ argument
56 mov reg, tmp; \
62 sllx tmp, 7, tmp; \
63 wr tmp, 0, %asr27; \
64 clr tmp; \
66 brnz,pt tmp, 88b; \
67 sub tmp, 1, tmp; \
68 set BACKOFF_LIMIT, tmp; \
69 cmp reg, tmp; \
82 #define BACKOFF_SPIN(reg, tmp, label) argument
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| /arch/m68k/include/asm/ |
| D | raw_io.h | 112 unsigned int tmp; in raw_outsb() local
115 tmp = (nr & 15) - 1; in raw_outsb()
118 : "=a" (buf), "=d" (tmp) in raw_outsb()
120 "1" (tmp)); in raw_outsb()
123 tmp = (nr >> 4) - 1; in raw_outsb()
143 : "=a" (buf), "=d" (tmp) in raw_outsb()
145 "1" (tmp)); in raw_outsb()
151 unsigned int tmp; in raw_insw() local
154 tmp = (nr & 15) - 1; in raw_insw()
157 : "=a" (buf), "=d" (tmp) in raw_insw()
[all …]
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| /arch/arm64/include/asm/ |
| D | assembler.h | 74 .macro disable_step_tsk, flgs, tmp
76 mrs \tmp, mdscr_el1
77 bic \tmp, \tmp, #DBG_MDSCR_SS
78 msr mdscr_el1, \tmp
84 .macro enable_step_tsk, flgs, tmp
86 mrs \tmp, mdscr_el1
87 orr \tmp, \tmp, #DBG_MDSCR_SS
88 msr mdscr_el1, \tmp
217 .macro ldr_l, dst, sym, tmp=
218 .ifb \tmp
[all …]
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| /arch/arm/mach-exynos/ |
| D | pm.c | 52 unsigned long tmp; in exynos_cpu_save_register() local
56 : "=r" (tmp) : : "cc"); in exynos_cpu_save_register()
58 save_arm_register[0] = tmp; in exynos_cpu_save_register()
62 : "=r" (tmp) : : "cc"); in exynos_cpu_save_register()
64 save_arm_register[1] = tmp; in exynos_cpu_save_register()
69 unsigned long tmp; in exynos_cpu_restore_register() local
72 tmp = save_arm_register[0]; in exynos_cpu_restore_register()
75 : : "r" (tmp) in exynos_cpu_restore_register()
79 tmp = save_arm_register[1]; in exynos_cpu_restore_register()
82 : : "r" (tmp) in exynos_cpu_restore_register()
[all …]
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| /arch/powerpc/platforms/pseries/ |
| D | reconfig.c | 117 char *tmp; in parse_next_property() local
121 tmp = strchr(buf, ' '); in parse_next_property()
122 if (!tmp) { in parse_next_property()
127 *tmp = '\0'; in parse_next_property()
129 if (++tmp >= end) { in parse_next_property()
137 *length = simple_strtoul(tmp, &tmp, 10); in parse_next_property()
143 if (*tmp != ' ' || ++tmp >= end) { in parse_next_property()
150 *value = tmp; in parse_next_property()
151 tmp += *length; in parse_next_property()
152 if (tmp > end) { in parse_next_property()
[all …]
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| /arch/m68k/mm/ |
| D | memory.c | 103 int tmp; in cache_clear() local
110 if ((tmp = -paddr & (PAGE_SIZE - 1))) { in cache_clear()
112 if ((len -= tmp) <= 0) in cache_clear()
114 paddr += tmp; in cache_clear()
116 tmp = PAGE_SIZE; in cache_clear()
118 while ((len -= tmp) >= 0) { in cache_clear()
120 paddr += tmp; in cache_clear()
122 if ((len += tmp)) in cache_clear()
152 int tmp = PAGE_SIZE; in cache_push() local
169 paddr += tmp; in cache_push()
[all …]
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| /arch/openrisc/include/asm/bitops/ |
| D | atomic.h | 16 unsigned long tmp; in set_bit() local
24 : "=&r"(tmp) in set_bit()
33 unsigned long tmp; in clear_bit() local
41 : "=&r"(tmp) in clear_bit()
50 unsigned long tmp; in change_bit() local
58 : "=&r"(tmp) in change_bit()
68 unsigned long tmp; in test_and_set_bit() local
76 : "=&r"(old), "=&r"(tmp) in test_and_set_bit()
88 unsigned long tmp; in test_and_clear_bit() local
96 : "=&r"(old), "=&r"(tmp) in test_and_clear_bit()
[all …]
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| /arch/arm/mach-s5pv210/ |
| D | pm.c | 86 unsigned long tmp; in s5pv210_cpu_suspend() local
91 tmp = 0; in s5pv210_cpu_suspend()
98 "wfi" : : "r" (tmp)); in s5pv210_cpu_suspend()
106 unsigned int tmp; in s5pv210_pm_prepare() local
117 tmp = __raw_readl(S5P_SLEEP_CFG); in s5pv210_pm_prepare()
118 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); in s5pv210_pm_prepare()
119 __raw_writel(tmp, S5P_SLEEP_CFG); in s5pv210_pm_prepare()
122 tmp = __raw_readl(S5P_PWR_CFG); in s5pv210_pm_prepare()
123 tmp &= S5P_CFG_WFI_CLEAN; in s5pv210_pm_prepare()
124 tmp |= S5P_CFG_WFI_SLEEP; in s5pv210_pm_prepare()
[all …]
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