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/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dts22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
39 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
40 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
41 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
45 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
[all …]
Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
37 reg = <0x0 0x0 0x02000000>;
69 ranges = <0x0 0x0 0xe0000000 0x100000>;
128 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
[all …]
Dmpc8572ds.dts21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
36 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
37 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
[all …]
Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
35 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
[all …]
Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
43 reg = <0x0 0x0 0x02000000>;
103 ranges = <0x0 0x0 0xe0000000 0x100000>;
143 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
[all …]
Dmpc8548cds.dtsi40 reg = <0x0 0x0 0x01000000>;
45 reg = <0x0 0x0b00000>;
74 reg = <0x1 0x0 0x1000>;
111 reg = <0x0>;
169 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
172 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
173 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
174 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
175 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
178 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
[all …]
Dmpc8572ds_36b.dts21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
36 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
37 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
[all …]
Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
41 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
43 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
47 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
[all …]
Dp1021mds.dts23 reg = <0x0 0xffe05000 0x0 0x1000>;
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
27 0x1 0x0 0x0 0xf8000000 0x00008000
28 0x2 0x0 0x0 0xf8010000 0x00020000
29 0x3 0x0 0x0 0xf8020000 0x00020000>;
36 reg = <0x0 0x0 0x40000>;
41 reg = <0x0 0x00100000>;
108 ranges = <0x0 0x0 0xffe00000 0x100000>;
156 reg = <0x0>;
198 ranges = <0x0 0xe0100 0x60>;
[all …]
Dmpc8572ds.dtsi40 reg = <0x0 0x0 0x8000000>;
45 reg = <0x0 0x03000000>;
94 reg = <0x2 0x0 0x40000>;
97 reg = <0x0 0x02000000>;
131 reg = <0x4 0x0 0x40000>;
137 reg = <0x5 0x0 0x40000>;
143 reg = <0x6 0x0 0x40000>;
157 reg = <0x0>;
247 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
250 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
Dp1020rdb.dts21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
35 ranges = <0x2000000 0x0 0xa0000000
36 0x2000000 0x0 0xa0000000
37 0x0 0x20000000
39 0x1000000 0x0 0x0
[all …]
Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
41 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
43 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
47 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
48 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
[all …]
Dmpc8540ads.dts33 reg = <0x0>;
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <0x0 0x1000>;
103 ranges = <0x0 0x21100 0x200>;
108 reg = <0x0 0x80>;
147 ranges = <0x0 0x24000 0x1000>;
163 reg = <0x0>;
190 ranges = <0x0 0x25000 0x1000>;
218 ranges = <0x0 0x26000 0x1000>;
[all …]
Dp1020rdb_36b.dts21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
35 ranges = <0x2000000 0x0 0xc0000000
36 0x2000000 0x0 0xc0000000
37 0x0 0x20000000
39 0x1000000 0x0 0x0
[all …]
Dp1025twr.dtsi47 reg = <0x0 0x0 0x4000000>;
54 reg = <0x0 0x00040000>;
172 ranges = <0x0 0xe0100 0x60>;
178 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
179 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
180 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
181 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
182 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
183 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
184 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
[all …]
/arch/x86/platform/ce4100/
Dfalconfalls.dts57 0x0000000 0 0x0 0x0 0 0x100>;
64 reg = <0x100 0x0 0x0 0x0 0x0>;
65 assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
74 reg = <0x0800 0x0 0x0 0x0 0x0>;
85 reg = <0x11000 0x0 0x0 0x0 0x0>;
95 reg = <0x11800 0x0 0x0 0x0 0x0>;
105 reg = <0x12000 0x0 0x0 0x0 0x0>;
115 reg = <0x12100 0x0 0x0 0x0 0x0>;
125 reg = <0x13000 0x0 0x0 0x0 0x0>;
135 reg = <0x13100 0x0 0x0 0x0 0x0>;
[all …]
/arch/arm64/include/asm/
Del2_setup.h20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF
21 msr sctlr_el2, x0
36 mrs x0, cnthctl_el2
37 orr x0, x0, #3 // Enable EL1 physical timers
38 msr cnthctl_el2, x0
44 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
45 cmp x0, #1
47 mrs x0, pmcr_el0 // Disable debug access traps
48 ubfx x0, x0, #11, #5 // to EL2 and allow access to
50 csel x2, xzr, x0, lt // all PMU counters from EL1
[all …]
/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi21 reg = <0x0 0x000>;
31 reg = <0x0 0x001>;
41 reg = <0x0 0x100>;
51 reg = <0x0 0x101>;
61 reg = <0x0 0x200>;
71 reg = <0x0 0x201>;
81 reg = <0x0 0x300>;
91 reg = <0x0 0x301>;
119 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
[all …]
Dapm-storm.dtsi21 reg = <0x0 0x000>;
29 reg = <0x0 0x001>;
37 reg = <0x0 0x100>;
45 reg = <0x0 0x101>;
53 reg = <0x0 0x200>;
61 reg = <0x0 0x201>;
69 reg = <0x0 0x300>;
77 reg = <0x0 0x301>;
100 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
101 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
[all …]
/arch/mips/boot/dts/loongson/
Dls7a-pch.dtsi72 ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
73 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
81 reg = <0x2000 0x0 0x0 0x0 0x0>;
92 reg = <0x2100 0x0 0x0 0x0 0x0>;
103 reg = <0x2800 0x0 0x0 0x0 0x0>;
114 reg = <0x2900 0x0 0x0 0x0 0x0>;
125 reg = <0x4000 0x0 0x0 0x0 0x0>;
136 reg = <0x4100 0x0 0x0 0x0 0x0>;
147 reg = <0x4200 0x0 0x0 0x0 0x0>;
158 reg = <0x3000 0x0 0x0 0x0 0x0>;
[all …]
/arch/powerpc/boot/dts/
Dmpc834x_mds.dts31 reg = <0x0>;
57 ranges = <0x0 0xe0000000 0x00100000>;
174 ranges = <0x0 0x24000 0x1000>;
191 reg = <0x0>;
215 ranges = <0x0 0x25000 0x1000>;
283 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
287 0x8800 0x0 0x0 0x1 &ipic 20 0x8
288 0x8800 0x0 0x0 0x2 &ipic 21 0x8
289 0x8800 0x0 0x0 0x3 &ipic 22 0x8
290 0x8800 0x0 0x0 0x4 &ipic 23 0x8
[all …]
Dmpc7448hpc2.dts33 reg = <0x0>;
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
147 ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
148 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
152 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
156 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
157 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
158 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
159 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
[all …]
/arch/arm/boot/dts/
Dimx27-eukrea-cpuimx27.dtsi160 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
161 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
162 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
163 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
164 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
165 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
166 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
167 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
168 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
169 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
[all …]
Dimx27-pdk.dts122 MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
123 MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
124 MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
125 MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */
126 MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */
132 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
133 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
134 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
135 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
136 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
[all …]
/arch/arm64/kernel/
Dhyp-stub.S49 cmp x0, #HVC_SET_VECTORS
54 1: cmp x0, #HVC_VHE_RESTART
57 2: cmp x0, #HVC_SOFT_RESTART
59 mov x0, x2
65 3: cmp x0, #HVC_RESET_VECTORS
69 mov_q x0, HVC_STUB_ERR
72 9: mov x0, xzr
98 1: mov_q x0, HVC_STUB_ERR
102 mov_q x0, HCR_HOST_VHE_FLAGS
103 msr hcr_el2, x0
[all …]

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