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/arch/x86/crypto/
Dserpent-avx2-asm_64.S61 #define S0_1(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x3, tp; \
63 vpxor x3, x0, x0; \
64 vpxor x2, x3, x4; \
66 vpxor x1, tp, x3; \
70 #define S0_2(x0, x1, x2, x3, x4) \ argument
71 vpxor x3, x0, x0; \
75 vpxor x2, x3, x3; \
80 #define S1_1(x0, x1, x2, x3, x4) \ argument
82 vpxor x3, x0, x0; \
[all …]
Dserpent-avx-x86_64-asm_64.S55 #define S0_1(x0, x1, x2, x3, x4) \ argument
56 vpor x0, x3, tp; \
57 vpxor x3, x0, x0; \
58 vpxor x2, x3, x4; \
60 vpxor x1, tp, x3; \
64 #define S0_2(x0, x1, x2, x3, x4) \ argument
65 vpxor x3, x0, x0; \
69 vpxor x2, x3, x3; \
74 #define S1_1(x0, x1, x2, x3, x4) \ argument
76 vpxor x3, x0, x0; \
[all …]
Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
Dserpent-sse2-i586-asm_32.S42 #define K(x0, x1, x2, x3, x4, i) \ argument
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
72 pslld $7, x3; \
74 por x4, x3; \
78 pxor x3, x0; \
79 pxor x3, x2; \
[all …]
Dglue_helper-asm-avx.S8 #define load_8way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
12 vmovdqu (3*16)(src), x3; \
18 #define store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
22 vmovdqu x3, (3*16)(dst); \
28 #define store_cbc_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
31 vpxor (2*16)(src), x3, x3; \
36 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
44 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \ argument
59 vpshufb t1, x7, x3; \
72 #define store_ctr_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
[all …]
Dglue_helper-asm-avx2.S8 #define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
12 vmovdqu (3*32)(src), x3; \
18 #define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
22 vmovdqu x3, (3*32)(dst); \
28 #define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \ argument
34 vpxor (2*32+16)(src), x3, x3; \
39 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
55 #define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \ argument
75 vpshufb t1, t2, x3; \
88 #define store_ctr_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
[all …]
Dchacha-avx512vl-x86_64.S56 # x0 += x1, x3 = rotl32(x3 ^ x0, 16)
61 # x2 += x3, x1 = rotl32(x1 ^ x2, 12)
66 # x0 += x1, x3 = rotl32(x3 ^ x0, 8)
71 # x2 += x3, x1 = rotl32(x1 ^ x2, 7)
80 # x3 = shuffle32(x3, MASK(2, 1, 0, 3))
83 # x0 += x1, x3 = rotl32(x3 ^ x0, 16)
88 # x2 += x3, x1 = rotl32(x1 ^ x2, 12)
93 # x0 += x1, x3 = rotl32(x3 ^ x0, 8)
98 # x2 += x3, x1 = rotl32(x1 ^ x2, 7)
107 # x3 = shuffle32(x3, MASK(0, 3, 2, 1))
[all …]
/arch/arm64/lib/
Dtishift.S12 mov x3, #64
13 sub x3, x3, x2
14 cmp x3, #0
17 lsr x3, x0, x3
19 orr x1, x1, x3
34 mov x3, #64
35 sub x3, x3, x2
36 cmp x3, #0
39 lsl x3, x1, x3
41 orr x0, x0, x3
[all …]
Dcrc32.S23 ldp x3, x4, [x1]
27 CPU_BE( rev x3, x3 )
33 crc32\c\()x w8, w0, x3
34 csel x3, x3, x4, eq
37 lsr x4, x3, #32
39 csel x3, x3, x4, eq
55 32: ldp x3, x4, [x1], #32
58 CPU_BE( rev x3, x3 )
62 crc32\c\()x w0, w0, x3
70 ldr x3, [x1], #8
[all …]
Dmte.S72 mov x3, x1
74 1: ldgm x4, [x3]
77 add x3, x3, x5
93 mov x3, x1
104 2: sub x0, x1, x3 // update the number of tags set
118 mov x3, x0
130 2: sub x0, x0, x3 // update the number of tags copied
Dstrrchr.S22 mov x3, #0
28 sub x3, x0, #1
30 2: mov x0, x3
/arch/arm64/mm/
Dcache.S41 uaccess_ttbr0_enable x2, x3, x4
46 dcache_line_size x2, x3
47 sub x3, x2, #1
48 bic x4, x0, x3
61 invalidate_icache_by_line x0, x1, x2, x3, 9f
87 uaccess_ttbr0_enable x2, x3, x4
89 invalidate_icache_by_line x0, x1, x2, x3, 2f
109 dcache_by_line_op civac, sy, x0, x1, x2, x3
127 dcache_by_line_op cvau, ish, x0, x1, x2, x3
151 dcache_line_size x2, x3
[all …]
/arch/powerpc/boot/dts/fsl/
Dmpc8548cds.dtsi123 reg = <0x3>;
174 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
175 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
180 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
185 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
186 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
192 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
193 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
198 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
199 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
[all …]
Dmpc8540ads.dts173 reg = <0x3>;
274 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
280 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
281 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
284 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
286 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
291 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
292 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
298 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
304 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
[all …]
Dmpc8572ds.dtsi169 reg = <0x3>;
251 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
252 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
257 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
258 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
263 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
264 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
269 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
270 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
275 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
[all …]
Dmpc8560ads.dts167 reg = <0x3>;
313 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
316 /* IDSEL 0x3 */
319 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
320 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
323 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
325 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
330 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
331 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
337 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
[all …]
Dmpc8569mds.dts35 0x3 0x0 0x0 0xfc000000 0x00008000
144 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
146 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
147 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
149 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
150 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
155 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
164 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
165 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
175 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
[all …]
/arch/arm64/kvm/hyp/
Dentry.S66 ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)]
115 stp x2, x3, [x1, #CPU_XREG_OFFSET(2)]
118 ldp x2, x3, [sp], #16 // x0, x1
121 stp x2, x3, [x1, #CPU_XREG_OFFSET(0)]
136 adr_this_cpu x2, kvm_hyp_ctxt, x3
143 ptrauth_switch_to_hyp x1, x2, x3, x4, x5
146 restore_sp_el0 x2, x3
151 set_loaded_vcpu xzr, x2, x3
177 mrs x3, esr_el2
204 msr esr_el2, x3
/arch/sparc/include/asm/
Dsfp-machine_32.h108 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ argument
120 : "%rJ" ((USItype)(x3)), \
133 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ argument
145 : "%rJ" ((USItype)(x3)), \
160 #define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y… argument
162 #define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \ argument
167 : "=&r" (x3), \
172 "0" ((USItype)(x3)), \
/arch/arm64/kvm/hyp/nvhe/
Dhost.S19 stp x2, x3, [x0, #CPU_XREG_OFFSET(2)]
22 ldp x2, x3, [sp], #16 // x0, x1
25 stp x2, x3, [x0, #CPU_XREG_OFFSET(0)]
44 ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)]
93 mov x6, x3
94 get_vcpu_ptr x7, x3
95 mrs x3, esr_el2
158 mrs x3, par_el1
209 ldp x2, x3, [x18, #CPU_XREG_OFFSET(2)]
221 stp x2, x3, [x18, #CPU_XREG_OFFSET(2)]
Dhyp-init.S60 mov x3, #KVM_HOST_SMCCC_FUNC(__kvm_hyp_init)
61 cmp x0, x3
68 mov x3, lr
70 mov lr, x3
208 mov x1, x3
248 bic x3, x2, #SCTLR_ELx_M
249 msr sctlr_el2, x3
255 ldr x3, [x0, #NVHE_INIT_PGD_PA]
256 phys_to_ttbr x4, x3
/arch/powerpc/boot/dts/
DkuroboxHG.dts132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
137 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
140 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
141 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
142 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
143 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
DkuroboxHD.dts132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
137 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
140 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
141 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
142 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
143 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
/arch/arm64/kernel/
Dhibernate-asm.S81 mov x19, x3
87 copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
91 raw_dcache_line_size x2, x3
92 sub x3, x2, #1
93 bic x4, x10, x3
/arch/arm/crypto/
Daes-neonbs-core.S151 .macro mul_gf4_n_gf4, x0, x1, y0, y1, t0, x2, x3, y2, y3, t1
157 veor \x2, \x2, \x3
159 vand \x3, \x3, \y2
163 veor \x2, \x2, \x3
165 veor \x3, \x3, \t1
168 .macro mul_gf16_2, x0, x1, x2, x3, x4, x5, x6, x7, \
171 veor \t1, \x1, \x3
175 mul_gf4_n_gf4 \t0, \t1, \y0, \y1, \t3, \x2, \x3, \y2, \y3, \t2
179 veor \x3, \x3, \t1
192 .macro inv_gf256, x0, x1, x2, x3, x4, x5, x6, x7, \
[all …]

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