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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_nv.c247 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
301 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
Dmxgpu_ai.c230 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
278 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
Dmxgpu_vi.c505 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
535 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
Dnbio_v7_4.c382 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
418 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
Dsi_dma.c602 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
618 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
Damdgpu_irq.c473 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
Dsdma_v2_4.c1019 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1035 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
Dvce_v2_0.c525 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
Dcik_sdma.c1123 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1139 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
Dgmc_v9_0.c446 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
495 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
Dsdma_v3_0.c1353 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1369 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
Dgfx_v9_0.c5649 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5652 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5701 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
5719 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
5722 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
5738 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
5741 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
5772 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
Dgmc_v6_0.c1057 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
Dgfx_v6_0.c3245 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3274 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3308 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3333 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
Dvce_v3_0.c709 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
Dgmc_v10_0.c79 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
Ddce_v8_0.c2904 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
2955 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
2983 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
Dgfx_v7_0.c4731 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4782 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4805 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()
4830 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
Dvce_v4_0.c1015 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
Ddce_v10_0.c2993 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()
3022 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()
3051 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
Dsdma_v4_0.c2062 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()
2147 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_ecc_irq_state()
Ddce_v11_0.c3119 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()
3148 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vline_interrupt_state()
3177 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_hpd_irq_state()
Dgmc_v7_0.c1251 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v7_0_vm_fault_interrupt_state()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_irq.c640 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
671 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()

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