Searched refs:CCR2 (Results 1 – 2 of 2) sorted by relevance
| /drivers/char/pcmcia/ |
| D | synclink_cs.c | 270 #define CCR2 0x2e macro
2897 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; in mgslpc_set_rate()
2899 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
2966 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2968 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3001 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3002 write_reg(info, CHA + CCR2, val); in loopback_enable()
3135 write_reg(info, CHA + CCR2, val); in hdlc_mode()
3452 write_reg(info, CHA + CCR2, 0x10); in async_mode()
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| /drivers/dma/ti/ |
| D | omap-dma.c | 589 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
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