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Searched refs:CLK_LOW_FREQ (Results 1 – 7 of 7) sorted by relevance

/drivers/misc/cardreader/
Drts5228.c163 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5228_sd_set_sample_push_timing_sd30()
166 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5228_sd_set_sample_push_timing_sd30()
673 CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5228_pci_switch_clock()
698 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5228_pci_switch_clock()
Drts5261.c159 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5261_sd_set_sample_push_timing_sd30()
162 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_sd_set_sample_push_timing_sd30()
703 CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5261_pci_switch_clock()
728 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_pci_switch_clock()
Drts5260.c168 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing_sd30()
171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing_sd30()
Drtsx_pcr.c778 CLK_LOW_FREQ, CLK_LOW_FREQ); in rtsx_pci_switch_clock()
799 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
/drivers/mmc/host/
Drtsx_pci_sdmmc.c999 CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_timing()
1002 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1011 CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_timing()
1014 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1027 CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_timing()
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1041 CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_timing()
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
/drivers/staging/rts5208/
Drtsx_card.c665 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
683 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); in switch_ssc_clock()
778 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); in switch_normal_clock()
Drtsx_card.h49 #define CLK_LOW_FREQ 0x01 macro