1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DAL_DDC_SERVICE_TYPES_H__ 26 #define __DAL_DDC_SERVICE_TYPES_H__ 27 28 /* 0010FA dongles (ST Micro) external converter chip id */ 29 #define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA 30 /* 0022B9 external converter chip id */ 31 #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9 32 #define DP_BRANCH_DEVICE_ID_00001A 0x00001A 33 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1 34 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24 35 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C 36 37 enum ddc_result { 38 DDC_RESULT_UNKNOWN = 0, 39 DDC_RESULT_SUCESSFULL, 40 DDC_RESULT_FAILED_CHANNEL_BUSY, 41 DDC_RESULT_FAILED_TIMEOUT, 42 DDC_RESULT_FAILED_PROTOCOL_ERROR, 43 DDC_RESULT_FAILED_NACK, 44 DDC_RESULT_FAILED_INCOMPLETE, 45 DDC_RESULT_FAILED_OPERATION, 46 DDC_RESULT_FAILED_INVALID_OPERATION, 47 DDC_RESULT_FAILED_BUFFER_OVERFLOW, 48 DDC_RESULT_FAILED_HPD_DISCON 49 }; 50 51 enum ddc_service_type { 52 DDC_SERVICE_TYPE_CONNECTOR, 53 DDC_SERVICE_TYPE_DISPLAY_PORT_MST, 54 }; 55 56 /** 57 * display sink capability 58 */ 59 struct display_sink_capability { 60 /* dongle type (DP converter, CV smart dongle) */ 61 enum display_dongle_type dongle_type; 62 63 /********************************************************** 64 capabilities going INTO SINK DEVICE (stream capabilities) 65 **********************************************************/ 66 /* Dongle's downstream count. */ 67 uint32_t downstrm_sink_count; 68 /* Is dongle's downstream count info field (downstrm_sink_count) 69 * valid. */ 70 bool downstrm_sink_count_valid; 71 72 /* Maximum additional audio delay in microsecond (us) */ 73 uint32_t additional_audio_delay; 74 /* Audio latency value in microsecond (us) */ 75 uint32_t audio_latency; 76 /* Interlace video latency value in microsecond (us) */ 77 uint32_t video_latency_interlace; 78 /* Progressive video latency value in microsecond (us) */ 79 uint32_t video_latency_progressive; 80 /* Dongle caps: Maximum pixel clock supported over dongle for HDMI */ 81 uint32_t max_hdmi_pixel_clock; 82 /* Dongle caps: Maximum deep color supported over dongle for HDMI */ 83 enum dc_color_depth max_hdmi_deep_color; 84 85 /************************************************************ 86 capabilities going OUT OF SOURCE DEVICE (link capabilities) 87 ************************************************************/ 88 /* support for Spread Spectrum(SS) */ 89 bool ss_supported; 90 /* DP link settings (laneCount, linkRate, Spread) */ 91 uint32_t dp_link_lane_count; 92 uint32_t dp_link_rate; 93 uint32_t dp_link_spead; 94 95 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 96 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 97 bool is_dp_hdmi_s3d_converter; 98 /* to check if we have queried the display capability 99 * for eDP panel already. */ 100 bool is_edp_sink_cap_valid; 101 102 enum ddc_transaction_type transaction_type; 103 enum signal_type signal; 104 }; 105 106 struct av_sync_data { 107 uint8_t av_granularity;/* DPCD 00023h */ 108 uint8_t aud_dec_lat1;/* DPCD 00024h */ 109 uint8_t aud_dec_lat2;/* DPCD 00025h */ 110 uint8_t aud_pp_lat1;/* DPCD 00026h */ 111 uint8_t aud_pp_lat2;/* DPCD 00027h */ 112 uint8_t vid_inter_lat;/* DPCD 00028h */ 113 uint8_t vid_prog_lat;/* DPCD 00029h */ 114 uint8_t aud_del_ins1;/* DPCD 0002Bh */ 115 uint8_t aud_del_ins2;/* DPCD 0002Ch */ 116 uint8_t aud_del_ins3;/* DPCD 0002Dh */ 117 }; 118 119 /*Travis*/ 120 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; 121 /*Nutmeg*/ 122 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; 123 /*DP to Dual link DVI converter*/ 124 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; 125 126 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ 127