1 #ifndef A6XX_XML
2 #define A6XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24
25 Copyright (C) 2013-2020 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a6xx_tile_mode {
52 TILE6_LINEAR = 0,
53 TILE6_2 = 2,
54 TILE6_3 = 3,
55 };
56
57 enum a6xx_format {
58 FMT6_A8_UNORM = 2,
59 FMT6_8_UNORM = 3,
60 FMT6_8_SNORM = 4,
61 FMT6_8_UINT = 5,
62 FMT6_8_SINT = 6,
63 FMT6_4_4_4_4_UNORM = 8,
64 FMT6_5_5_5_1_UNORM = 10,
65 FMT6_1_5_5_5_UNORM = 12,
66 FMT6_5_6_5_UNORM = 14,
67 FMT6_8_8_UNORM = 15,
68 FMT6_8_8_SNORM = 16,
69 FMT6_8_8_UINT = 17,
70 FMT6_8_8_SINT = 18,
71 FMT6_L8_A8_UNORM = 19,
72 FMT6_16_UNORM = 21,
73 FMT6_16_SNORM = 22,
74 FMT6_16_FLOAT = 23,
75 FMT6_16_UINT = 24,
76 FMT6_16_SINT = 25,
77 FMT6_8_8_8_UNORM = 33,
78 FMT6_8_8_8_SNORM = 34,
79 FMT6_8_8_8_UINT = 35,
80 FMT6_8_8_8_SINT = 36,
81 FMT6_8_8_8_8_UNORM = 48,
82 FMT6_8_8_8_X8_UNORM = 49,
83 FMT6_8_8_8_8_SNORM = 50,
84 FMT6_8_8_8_8_UINT = 51,
85 FMT6_8_8_8_8_SINT = 52,
86 FMT6_9_9_9_E5_FLOAT = 53,
87 FMT6_10_10_10_2_UNORM = 54,
88 FMT6_10_10_10_2_UNORM_DEST = 55,
89 FMT6_10_10_10_2_SNORM = 57,
90 FMT6_10_10_10_2_UINT = 58,
91 FMT6_10_10_10_2_SINT = 59,
92 FMT6_11_11_10_FLOAT = 66,
93 FMT6_16_16_UNORM = 67,
94 FMT6_16_16_SNORM = 68,
95 FMT6_16_16_FLOAT = 69,
96 FMT6_16_16_UINT = 70,
97 FMT6_16_16_SINT = 71,
98 FMT6_32_UNORM = 72,
99 FMT6_32_SNORM = 73,
100 FMT6_32_FLOAT = 74,
101 FMT6_32_UINT = 75,
102 FMT6_32_SINT = 76,
103 FMT6_32_FIXED = 77,
104 FMT6_16_16_16_UNORM = 88,
105 FMT6_16_16_16_SNORM = 89,
106 FMT6_16_16_16_FLOAT = 90,
107 FMT6_16_16_16_UINT = 91,
108 FMT6_16_16_16_SINT = 92,
109 FMT6_16_16_16_16_UNORM = 96,
110 FMT6_16_16_16_16_SNORM = 97,
111 FMT6_16_16_16_16_FLOAT = 98,
112 FMT6_16_16_16_16_UINT = 99,
113 FMT6_16_16_16_16_SINT = 100,
114 FMT6_32_32_UNORM = 101,
115 FMT6_32_32_SNORM = 102,
116 FMT6_32_32_FLOAT = 103,
117 FMT6_32_32_UINT = 104,
118 FMT6_32_32_SINT = 105,
119 FMT6_32_32_FIXED = 106,
120 FMT6_32_32_32_UNORM = 112,
121 FMT6_32_32_32_SNORM = 113,
122 FMT6_32_32_32_UINT = 114,
123 FMT6_32_32_32_SINT = 115,
124 FMT6_32_32_32_FLOAT = 116,
125 FMT6_32_32_32_FIXED = 117,
126 FMT6_32_32_32_32_UNORM = 128,
127 FMT6_32_32_32_32_SNORM = 129,
128 FMT6_32_32_32_32_FLOAT = 130,
129 FMT6_32_32_32_32_UINT = 131,
130 FMT6_32_32_32_32_SINT = 132,
131 FMT6_32_32_32_32_FIXED = 133,
132 FMT6_G8R8B8R8_422_UNORM = 140,
133 FMT6_R8G8R8B8_422_UNORM = 141,
134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
135 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
136 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
137 FMT6_8_PLANE_UNORM = 148,
138 FMT6_Z24_UNORM_S8_UINT = 160,
139 FMT6_ETC2_RG11_UNORM = 171,
140 FMT6_ETC2_RG11_SNORM = 172,
141 FMT6_ETC2_R11_UNORM = 173,
142 FMT6_ETC2_R11_SNORM = 174,
143 FMT6_ETC1 = 175,
144 FMT6_ETC2_RGB8 = 176,
145 FMT6_ETC2_RGBA8 = 177,
146 FMT6_ETC2_RGB8A1 = 178,
147 FMT6_DXT1 = 179,
148 FMT6_DXT3 = 180,
149 FMT6_DXT5 = 181,
150 FMT6_RGTC1_UNORM = 183,
151 FMT6_RGTC1_SNORM = 184,
152 FMT6_RGTC2_UNORM = 187,
153 FMT6_RGTC2_SNORM = 188,
154 FMT6_BPTC_UFLOAT = 190,
155 FMT6_BPTC_FLOAT = 191,
156 FMT6_BPTC = 192,
157 FMT6_ASTC_4x4 = 193,
158 FMT6_ASTC_5x4 = 194,
159 FMT6_ASTC_5x5 = 195,
160 FMT6_ASTC_6x5 = 196,
161 FMT6_ASTC_6x6 = 197,
162 FMT6_ASTC_8x5 = 198,
163 FMT6_ASTC_8x6 = 199,
164 FMT6_ASTC_8x8 = 200,
165 FMT6_ASTC_10x5 = 201,
166 FMT6_ASTC_10x6 = 202,
167 FMT6_ASTC_10x8 = 203,
168 FMT6_ASTC_10x10 = 204,
169 FMT6_ASTC_12x10 = 205,
170 FMT6_ASTC_12x12 = 206,
171 FMT6_S8Z24_UINT = 234,
172 FMT6_NONE = 255,
173 };
174
175 enum a6xx_polygon_mode {
176 POLYMODE6_POINTS = 1,
177 POLYMODE6_LINES = 2,
178 POLYMODE6_TRIANGLES = 3,
179 };
180
181 enum a6xx_depth_format {
182 DEPTH6_NONE = 0,
183 DEPTH6_16 = 1,
184 DEPTH6_24_8 = 2,
185 DEPTH6_32 = 4,
186 };
187
188 enum a6xx_shader_id {
189 A6XX_TP0_TMO_DATA = 9,
190 A6XX_TP0_SMO_DATA = 10,
191 A6XX_TP0_MIPMAP_BASE_DATA = 11,
192 A6XX_TP1_TMO_DATA = 25,
193 A6XX_TP1_SMO_DATA = 26,
194 A6XX_TP1_MIPMAP_BASE_DATA = 27,
195 A6XX_SP_INST_DATA = 41,
196 A6XX_SP_LB_0_DATA = 42,
197 A6XX_SP_LB_1_DATA = 43,
198 A6XX_SP_LB_2_DATA = 44,
199 A6XX_SP_LB_3_DATA = 45,
200 A6XX_SP_LB_4_DATA = 46,
201 A6XX_SP_LB_5_DATA = 47,
202 A6XX_SP_CB_BINDLESS_DATA = 48,
203 A6XX_SP_CB_LEGACY_DATA = 49,
204 A6XX_SP_UAV_DATA = 50,
205 A6XX_SP_INST_TAG = 51,
206 A6XX_SP_CB_BINDLESS_TAG = 52,
207 A6XX_SP_TMO_UMO_TAG = 53,
208 A6XX_SP_SMO_TAG = 54,
209 A6XX_SP_STATE_DATA = 55,
210 A6XX_HLSQ_CHUNK_CVS_RAM = 73,
211 A6XX_HLSQ_CHUNK_CPS_RAM = 74,
212 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
213 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
214 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
215 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
216 A6XX_HLSQ_CVS_MISC_RAM = 80,
217 A6XX_HLSQ_CPS_MISC_RAM = 81,
218 A6XX_HLSQ_INST_RAM = 82,
219 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
220 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
221 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
222 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
223 A6XX_HLSQ_INST_RAM_TAG = 87,
224 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
225 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
226 A6XX_HLSQ_PWR_REST_RAM = 90,
227 A6XX_HLSQ_PWR_REST_TAG = 91,
228 A6XX_HLSQ_DATAPATH_META = 96,
229 A6XX_HLSQ_FRONTEND_META = 97,
230 A6XX_HLSQ_INDIRECT_META = 98,
231 A6XX_HLSQ_BACKEND_META = 99,
232 };
233
234 enum a6xx_debugbus_id {
235 A6XX_DBGBUS_CP = 1,
236 A6XX_DBGBUS_RBBM = 2,
237 A6XX_DBGBUS_VBIF = 3,
238 A6XX_DBGBUS_HLSQ = 4,
239 A6XX_DBGBUS_UCHE = 5,
240 A6XX_DBGBUS_DPM = 6,
241 A6XX_DBGBUS_TESS = 7,
242 A6XX_DBGBUS_PC = 8,
243 A6XX_DBGBUS_VFDP = 9,
244 A6XX_DBGBUS_VPC = 10,
245 A6XX_DBGBUS_TSE = 11,
246 A6XX_DBGBUS_RAS = 12,
247 A6XX_DBGBUS_VSC = 13,
248 A6XX_DBGBUS_COM = 14,
249 A6XX_DBGBUS_LRZ = 16,
250 A6XX_DBGBUS_A2D = 17,
251 A6XX_DBGBUS_CCUFCHE = 18,
252 A6XX_DBGBUS_GMU_CX = 19,
253 A6XX_DBGBUS_RBP = 20,
254 A6XX_DBGBUS_DCS = 21,
255 A6XX_DBGBUS_DBGC = 22,
256 A6XX_DBGBUS_CX = 23,
257 A6XX_DBGBUS_GMU_GX = 24,
258 A6XX_DBGBUS_TPFCHE = 25,
259 A6XX_DBGBUS_GBIF_GX = 26,
260 A6XX_DBGBUS_GPC = 29,
261 A6XX_DBGBUS_LARC = 30,
262 A6XX_DBGBUS_HLSQ_SPTP = 31,
263 A6XX_DBGBUS_RB_0 = 32,
264 A6XX_DBGBUS_RB_1 = 33,
265 A6XX_DBGBUS_UCHE_WRAPPER = 36,
266 A6XX_DBGBUS_CCU_0 = 40,
267 A6XX_DBGBUS_CCU_1 = 41,
268 A6XX_DBGBUS_VFD_0 = 56,
269 A6XX_DBGBUS_VFD_1 = 57,
270 A6XX_DBGBUS_VFD_2 = 58,
271 A6XX_DBGBUS_VFD_3 = 59,
272 A6XX_DBGBUS_SP_0 = 64,
273 A6XX_DBGBUS_SP_1 = 65,
274 A6XX_DBGBUS_TPL1_0 = 72,
275 A6XX_DBGBUS_TPL1_1 = 73,
276 A6XX_DBGBUS_TPL1_2 = 74,
277 A6XX_DBGBUS_TPL1_3 = 75,
278 };
279
280 enum a6xx_cp_perfcounter_select {
281 PERF_CP_ALWAYS_COUNT = 0,
282 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
283 PERF_CP_BUSY_CYCLES = 2,
284 PERF_CP_NUM_PREEMPTIONS = 3,
285 PERF_CP_PREEMPTION_REACTION_DELAY = 4,
286 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
287 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
288 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
289 PERF_CP_PREDICATED_DRAWS_KILLED = 8,
290 PERF_CP_MODE_SWITCH = 9,
291 PERF_CP_ZPASS_DONE = 10,
292 PERF_CP_CONTEXT_DONE = 11,
293 PERF_CP_CACHE_FLUSH = 12,
294 PERF_CP_LONG_PREEMPTIONS = 13,
295 PERF_CP_SQE_I_CACHE_STARVE = 14,
296 PERF_CP_SQE_IDLE = 15,
297 PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
298 PERF_CP_SQE_PM4_STARVE_SDS = 17,
299 PERF_CP_SQE_MRB_STARVE = 18,
300 PERF_CP_SQE_RRB_STARVE = 19,
301 PERF_CP_SQE_VSD_STARVE = 20,
302 PERF_CP_VSD_DECODE_STARVE = 21,
303 PERF_CP_SQE_PIPE_OUT_STALL = 22,
304 PERF_CP_SQE_SYNC_STALL = 23,
305 PERF_CP_SQE_PM4_WFI_STALL = 24,
306 PERF_CP_SQE_SYS_WFI_STALL = 25,
307 PERF_CP_SQE_T4_EXEC = 26,
308 PERF_CP_SQE_LOAD_STATE_EXEC = 27,
309 PERF_CP_SQE_SAVE_SDS_STATE = 28,
310 PERF_CP_SQE_DRAW_EXEC = 29,
311 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
312 PERF_CP_SQE_EXEC_PROFILED = 31,
313 PERF_CP_MEMORY_POOL_EMPTY = 32,
314 PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
315 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
316 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
317 PERF_CP_AHB_STALL_SQE_GMU = 36,
318 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
319 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
320 PERF_CP_CLUSTER0_EMPTY = 39,
321 PERF_CP_CLUSTER1_EMPTY = 40,
322 PERF_CP_CLUSTER2_EMPTY = 41,
323 PERF_CP_CLUSTER3_EMPTY = 42,
324 PERF_CP_CLUSTER4_EMPTY = 43,
325 PERF_CP_CLUSTER5_EMPTY = 44,
326 PERF_CP_PM4_DATA = 45,
327 PERF_CP_PM4_HEADERS = 46,
328 PERF_CP_VBIF_READ_BEATS = 47,
329 PERF_CP_VBIF_WRITE_BEATS = 48,
330 PERF_CP_SQE_INSTR_COUNTER = 49,
331 };
332
333 enum a6xx_rbbm_perfcounter_select {
334 PERF_RBBM_ALWAYS_COUNT = 0,
335 PERF_RBBM_ALWAYS_ON = 1,
336 PERF_RBBM_TSE_BUSY = 2,
337 PERF_RBBM_RAS_BUSY = 3,
338 PERF_RBBM_PC_DCALL_BUSY = 4,
339 PERF_RBBM_PC_VSD_BUSY = 5,
340 PERF_RBBM_STATUS_MASKED = 6,
341 PERF_RBBM_COM_BUSY = 7,
342 PERF_RBBM_DCOM_BUSY = 8,
343 PERF_RBBM_VBIF_BUSY = 9,
344 PERF_RBBM_VSC_BUSY = 10,
345 PERF_RBBM_TESS_BUSY = 11,
346 PERF_RBBM_UCHE_BUSY = 12,
347 PERF_RBBM_HLSQ_BUSY = 13,
348 };
349
350 enum a6xx_pc_perfcounter_select {
351 PERF_PC_BUSY_CYCLES = 0,
352 PERF_PC_WORKING_CYCLES = 1,
353 PERF_PC_STALL_CYCLES_VFD = 2,
354 PERF_PC_STALL_CYCLES_TSE = 3,
355 PERF_PC_STALL_CYCLES_VPC = 4,
356 PERF_PC_STALL_CYCLES_UCHE = 5,
357 PERF_PC_STALL_CYCLES_TESS = 6,
358 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
359 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
360 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
361 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
362 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
363 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
364 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
365 PERF_PC_STARVE_CYCLES_DI = 14,
366 PERF_PC_VIS_STREAMS_LOADED = 15,
367 PERF_PC_INSTANCES = 16,
368 PERF_PC_VPC_PRIMITIVES = 17,
369 PERF_PC_DEAD_PRIM = 18,
370 PERF_PC_LIVE_PRIM = 19,
371 PERF_PC_VERTEX_HITS = 20,
372 PERF_PC_IA_VERTICES = 21,
373 PERF_PC_IA_PRIMITIVES = 22,
374 PERF_PC_GS_PRIMITIVES = 23,
375 PERF_PC_HS_INVOCATIONS = 24,
376 PERF_PC_DS_INVOCATIONS = 25,
377 PERF_PC_VS_INVOCATIONS = 26,
378 PERF_PC_GS_INVOCATIONS = 27,
379 PERF_PC_DS_PRIMITIVES = 28,
380 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
381 PERF_PC_3D_DRAWCALLS = 30,
382 PERF_PC_2D_DRAWCALLS = 31,
383 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
384 PERF_TESS_BUSY_CYCLES = 33,
385 PERF_TESS_WORKING_CYCLES = 34,
386 PERF_TESS_STALL_CYCLES_PC = 35,
387 PERF_TESS_STARVE_CYCLES_PC = 36,
388 PERF_PC_TSE_TRANSACTION = 37,
389 PERF_PC_TSE_VERTEX = 38,
390 PERF_PC_TESS_PC_UV_TRANS = 39,
391 PERF_PC_TESS_PC_UV_PATCHES = 40,
392 PERF_PC_TESS_FACTOR_TRANS = 41,
393 };
394
395 enum a6xx_vfd_perfcounter_select {
396 PERF_VFD_BUSY_CYCLES = 0,
397 PERF_VFD_STALL_CYCLES_UCHE = 1,
398 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
399 PERF_VFD_STALL_CYCLES_SP_INFO = 3,
400 PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
401 PERF_VFD_STARVE_CYCLES_UCHE = 5,
402 PERF_VFD_RBUFFER_FULL = 6,
403 PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
404 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
405 PERF_VFD_NUM_ATTRIBUTES = 9,
406 PERF_VFD_UPPER_SHADER_FIBERS = 10,
407 PERF_VFD_LOWER_SHADER_FIBERS = 11,
408 PERF_VFD_MODE_0_FIBERS = 12,
409 PERF_VFD_MODE_1_FIBERS = 13,
410 PERF_VFD_MODE_2_FIBERS = 14,
411 PERF_VFD_MODE_3_FIBERS = 15,
412 PERF_VFD_MODE_4_FIBERS = 16,
413 PERF_VFD_TOTAL_VERTICES = 17,
414 PERF_VFDP_STALL_CYCLES_VFD = 18,
415 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
416 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
417 PERF_VFDP_STARVE_CYCLES_PC = 21,
418 PERF_VFDP_VS_STAGE_WAVES = 22,
419 };
420
421 enum a6xx_hlsq_perfcounter_select {
422 PERF_HLSQ_BUSY_CYCLES = 0,
423 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
424 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
425 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
426 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
427 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
428 PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
429 PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
430 PERF_HLSQ_QUADS = 8,
431 PERF_HLSQ_CS_INVOCATIONS = 9,
432 PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
433 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
434 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
435 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
436 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
437 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
438 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
439 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
440 PERF_HLSQ_STALL_CYCLES_VPC = 18,
441 PERF_HLSQ_PIXELS = 19,
442 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
443 };
444
445 enum a6xx_vpc_perfcounter_select {
446 PERF_VPC_BUSY_CYCLES = 0,
447 PERF_VPC_WORKING_CYCLES = 1,
448 PERF_VPC_STALL_CYCLES_UCHE = 2,
449 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
450 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
451 PERF_VPC_STALL_CYCLES_PC = 5,
452 PERF_VPC_STALL_CYCLES_SP_LM = 6,
453 PERF_VPC_STARVE_CYCLES_SP = 7,
454 PERF_VPC_STARVE_CYCLES_LRZ = 8,
455 PERF_VPC_PC_PRIMITIVES = 9,
456 PERF_VPC_SP_COMPONENTS = 10,
457 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
458 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
459 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
460 PERF_VPC_LM_TRANSACTION = 14,
461 PERF_VPC_STREAMOUT_TRANSACTION = 15,
462 PERF_VPC_VS_BUSY_CYCLES = 16,
463 PERF_VPC_PS_BUSY_CYCLES = 17,
464 PERF_VPC_VS_WORKING_CYCLES = 18,
465 PERF_VPC_PS_WORKING_CYCLES = 19,
466 PERF_VPC_STARVE_CYCLES_RB = 20,
467 PERF_VPC_NUM_VPCRAM_READ_POS = 21,
468 PERF_VPC_WIT_FULL_CYCLES = 22,
469 PERF_VPC_VPCRAM_FULL_CYCLES = 23,
470 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
471 PERF_VPC_NUM_VPCRAM_WRITE = 25,
472 PERF_VPC_NUM_VPCRAM_READ_SO = 26,
473 PERF_VPC_NUM_ATTR_REQ_LM = 27,
474 };
475
476 enum a6xx_tse_perfcounter_select {
477 PERF_TSE_BUSY_CYCLES = 0,
478 PERF_TSE_CLIPPING_CYCLES = 1,
479 PERF_TSE_STALL_CYCLES_RAS = 2,
480 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
481 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
482 PERF_TSE_STARVE_CYCLES_PC = 5,
483 PERF_TSE_INPUT_PRIM = 6,
484 PERF_TSE_INPUT_NULL_PRIM = 7,
485 PERF_TSE_TRIVAL_REJ_PRIM = 8,
486 PERF_TSE_CLIPPED_PRIM = 9,
487 PERF_TSE_ZERO_AREA_PRIM = 10,
488 PERF_TSE_FACENESS_CULLED_PRIM = 11,
489 PERF_TSE_ZERO_PIXEL_PRIM = 12,
490 PERF_TSE_OUTPUT_NULL_PRIM = 13,
491 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
492 PERF_TSE_CINVOCATION = 15,
493 PERF_TSE_CPRIMITIVES = 16,
494 PERF_TSE_2D_INPUT_PRIM = 17,
495 PERF_TSE_2D_ALIVE_CYCLES = 18,
496 PERF_TSE_CLIP_PLANES = 19,
497 };
498
499 enum a6xx_ras_perfcounter_select {
500 PERF_RAS_BUSY_CYCLES = 0,
501 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
502 PERF_RAS_STALL_CYCLES_LRZ = 2,
503 PERF_RAS_STARVE_CYCLES_TSE = 3,
504 PERF_RAS_SUPER_TILES = 4,
505 PERF_RAS_8X4_TILES = 5,
506 PERF_RAS_MASKGEN_ACTIVE = 6,
507 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
508 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
509 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
510 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
511 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
512 PERF_RAS_BLOCKS = 12,
513 };
514
515 enum a6xx_uche_perfcounter_select {
516 PERF_UCHE_BUSY_CYCLES = 0,
517 PERF_UCHE_STALL_CYCLES_ARBITER = 1,
518 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
519 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
520 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
521 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
522 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
523 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
524 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
525 PERF_UCHE_READ_REQUESTS_TP = 9,
526 PERF_UCHE_READ_REQUESTS_VFD = 10,
527 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
528 PERF_UCHE_READ_REQUESTS_LRZ = 12,
529 PERF_UCHE_READ_REQUESTS_SP = 13,
530 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
531 PERF_UCHE_WRITE_REQUESTS_SP = 15,
532 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
533 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
534 PERF_UCHE_EVICTS = 18,
535 PERF_UCHE_BANK_REQ0 = 19,
536 PERF_UCHE_BANK_REQ1 = 20,
537 PERF_UCHE_BANK_REQ2 = 21,
538 PERF_UCHE_BANK_REQ3 = 22,
539 PERF_UCHE_BANK_REQ4 = 23,
540 PERF_UCHE_BANK_REQ5 = 24,
541 PERF_UCHE_BANK_REQ6 = 25,
542 PERF_UCHE_BANK_REQ7 = 26,
543 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
544 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
545 PERF_UCHE_GMEM_READ_BEATS = 29,
546 PERF_UCHE_TPH_REF_FULL = 30,
547 PERF_UCHE_TPH_VICTIM_FULL = 31,
548 PERF_UCHE_TPH_EXT_FULL = 32,
549 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
550 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
551 PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
552 PERF_UCHE_VBIF_READ_BEATS_PC = 36,
553 PERF_UCHE_READ_REQUESTS_PC = 37,
554 PERF_UCHE_RAM_READ_REQ = 38,
555 PERF_UCHE_RAM_WRITE_REQ = 39,
556 };
557
558 enum a6xx_tp_perfcounter_select {
559 PERF_TP_BUSY_CYCLES = 0,
560 PERF_TP_STALL_CYCLES_UCHE = 1,
561 PERF_TP_LATENCY_CYCLES = 2,
562 PERF_TP_LATENCY_TRANS = 3,
563 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
564 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
565 PERF_TP_L1_CACHELINE_REQUESTS = 6,
566 PERF_TP_L1_CACHELINE_MISSES = 7,
567 PERF_TP_SP_TP_TRANS = 8,
568 PERF_TP_TP_SP_TRANS = 9,
569 PERF_TP_OUTPUT_PIXELS = 10,
570 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
571 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
572 PERF_TP_QUADS_RECEIVED = 13,
573 PERF_TP_QUADS_OFFSET = 14,
574 PERF_TP_QUADS_SHADOW = 15,
575 PERF_TP_QUADS_ARRAY = 16,
576 PERF_TP_QUADS_GRADIENT = 17,
577 PERF_TP_QUADS_1D = 18,
578 PERF_TP_QUADS_2D = 19,
579 PERF_TP_QUADS_BUFFER = 20,
580 PERF_TP_QUADS_3D = 21,
581 PERF_TP_QUADS_CUBE = 22,
582 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
583 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
584 PERF_TP_OUTPUT_PIXELS_POINT = 25,
585 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
586 PERF_TP_OUTPUT_PIXELS_MIP = 27,
587 PERF_TP_OUTPUT_PIXELS_ANISO = 28,
588 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
589 PERF_TP_FLAG_CACHE_REQUESTS = 30,
590 PERF_TP_FLAG_CACHE_MISSES = 31,
591 PERF_TP_L1_5_L2_REQUESTS = 32,
592 PERF_TP_2D_OUTPUT_PIXELS = 33,
593 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
594 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
595 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
596 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
597 PERF_TP_TPA2TPC_TRANS = 38,
598 PERF_TP_L1_MISSES_ASTC_1TILE = 39,
599 PERF_TP_L1_MISSES_ASTC_2TILE = 40,
600 PERF_TP_L1_MISSES_ASTC_4TILE = 41,
601 PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
602 PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
603 PERF_TP_L1_BANK_CONFLICT = 44,
604 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
605 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
606 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
607 PERF_TP_FRONTEND_WORKING_CYCLES = 48,
608 PERF_TP_L1_TAG_WORKING_CYCLES = 49,
609 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
610 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
611 PERF_TP_BACKEND_WORKING_CYCLES = 52,
612 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
613 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
614 PERF_TP_STARVE_CYCLES_SP = 55,
615 PERF_TP_STARVE_CYCLES_UCHE = 56,
616 };
617
618 enum a6xx_sp_perfcounter_select {
619 PERF_SP_BUSY_CYCLES = 0,
620 PERF_SP_ALU_WORKING_CYCLES = 1,
621 PERF_SP_EFU_WORKING_CYCLES = 2,
622 PERF_SP_STALL_CYCLES_VPC = 3,
623 PERF_SP_STALL_CYCLES_TP = 4,
624 PERF_SP_STALL_CYCLES_UCHE = 5,
625 PERF_SP_STALL_CYCLES_RB = 6,
626 PERF_SP_NON_EXECUTION_CYCLES = 7,
627 PERF_SP_WAVE_CONTEXTS = 8,
628 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
629 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
630 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
631 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
632 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
633 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
634 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
635 PERF_SP_WAVE_CTRL_CYCLES = 16,
636 PERF_SP_WAVE_LOAD_CYCLES = 17,
637 PERF_SP_WAVE_EMIT_CYCLES = 18,
638 PERF_SP_WAVE_NOP_CYCLES = 19,
639 PERF_SP_WAVE_WAIT_CYCLES = 20,
640 PERF_SP_WAVE_FETCH_CYCLES = 21,
641 PERF_SP_WAVE_IDLE_CYCLES = 22,
642 PERF_SP_WAVE_END_CYCLES = 23,
643 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
644 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
645 PERF_SP_WAVE_JOIN_CYCLES = 26,
646 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
647 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
648 PERF_SP_LM_ATOMICS = 29,
649 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
650 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
651 PERF_SP_GM_ATOMICS = 32,
652 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
653 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
654 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
655 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
656 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
657 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
658 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
659 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
660 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
661 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
662 PERF_SP_VS_INSTRUCTIONS = 43,
663 PERF_SP_FS_INSTRUCTIONS = 44,
664 PERF_SP_ADDR_LOCK_COUNT = 45,
665 PERF_SP_UCHE_READ_TRANS = 46,
666 PERF_SP_UCHE_WRITE_TRANS = 47,
667 PERF_SP_EXPORT_VPC_TRANS = 48,
668 PERF_SP_EXPORT_RB_TRANS = 49,
669 PERF_SP_PIXELS_KILLED = 50,
670 PERF_SP_ICL1_REQUESTS = 51,
671 PERF_SP_ICL1_MISSES = 52,
672 PERF_SP_HS_INSTRUCTIONS = 53,
673 PERF_SP_DS_INSTRUCTIONS = 54,
674 PERF_SP_GS_INSTRUCTIONS = 55,
675 PERF_SP_CS_INSTRUCTIONS = 56,
676 PERF_SP_GPR_READ = 57,
677 PERF_SP_GPR_WRITE = 58,
678 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
679 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
680 PERF_SP_LM_BANK_CONFLICTS = 61,
681 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
682 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
683 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
684 PERF_SP_LM_WORKING_CYCLES = 65,
685 PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
686 PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
687 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
688 PERF_SP_STARVE_CYCLES_HLSQ = 69,
689 PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
690 PERF_SP_WORKING_EU = 71,
691 PERF_SP_ANY_EU_WORKING = 72,
692 PERF_SP_WORKING_EU_FS_STAGE = 73,
693 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
694 PERF_SP_WORKING_EU_VS_STAGE = 75,
695 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
696 PERF_SP_WORKING_EU_CS_STAGE = 77,
697 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
698 PERF_SP_GPR_READ_PREFETCH = 79,
699 PERF_SP_GPR_READ_CONFLICT = 80,
700 PERF_SP_GPR_WRITE_CONFLICT = 81,
701 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
702 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
703 PERF_SP_EXECUTABLE_WAVES = 84,
704 };
705
706 enum a6xx_rb_perfcounter_select {
707 PERF_RB_BUSY_CYCLES = 0,
708 PERF_RB_STALL_CYCLES_HLSQ = 1,
709 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
710 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
711 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
712 PERF_RB_STARVE_CYCLES_SP = 5,
713 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
714 PERF_RB_STARVE_CYCLES_CCU = 7,
715 PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
716 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
717 PERF_RB_Z_WORKLOAD = 10,
718 PERF_RB_HLSQ_ACTIVE = 11,
719 PERF_RB_Z_READ = 12,
720 PERF_RB_Z_WRITE = 13,
721 PERF_RB_C_READ = 14,
722 PERF_RB_C_WRITE = 15,
723 PERF_RB_TOTAL_PASS = 16,
724 PERF_RB_Z_PASS = 17,
725 PERF_RB_Z_FAIL = 18,
726 PERF_RB_S_FAIL = 19,
727 PERF_RB_BLENDED_FXP_COMPONENTS = 20,
728 PERF_RB_BLENDED_FP16_COMPONENTS = 21,
729 PERF_RB_PS_INVOCATIONS = 22,
730 PERF_RB_2D_ALIVE_CYCLES = 23,
731 PERF_RB_2D_STALL_CYCLES_A2D = 24,
732 PERF_RB_2D_STARVE_CYCLES_SRC = 25,
733 PERF_RB_2D_STARVE_CYCLES_SP = 26,
734 PERF_RB_2D_STARVE_CYCLES_DST = 27,
735 PERF_RB_2D_VALID_PIXELS = 28,
736 PERF_RB_3D_PIXELS = 29,
737 PERF_RB_BLENDER_WORKING_CYCLES = 30,
738 PERF_RB_ZPROC_WORKING_CYCLES = 31,
739 PERF_RB_CPROC_WORKING_CYCLES = 32,
740 PERF_RB_SAMPLER_WORKING_CYCLES = 33,
741 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
742 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
743 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
744 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
745 PERF_RB_STALL_CYCLES_VPC = 38,
746 PERF_RB_2D_INPUT_TRANS = 39,
747 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
748 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
749 PERF_RB_BLENDED_FP32_COMPONENTS = 42,
750 PERF_RB_COLOR_PIX_TILES = 43,
751 PERF_RB_STALL_CYCLES_CCU = 44,
752 PERF_RB_EARLY_Z_ARB3_GRANT = 45,
753 PERF_RB_LATE_Z_ARB3_GRANT = 46,
754 PERF_RB_EARLY_Z_SKIP_GRANT = 47,
755 };
756
757 enum a6xx_vsc_perfcounter_select {
758 PERF_VSC_BUSY_CYCLES = 0,
759 PERF_VSC_WORKING_CYCLES = 1,
760 PERF_VSC_STALL_CYCLES_UCHE = 2,
761 PERF_VSC_EOT_NUM = 3,
762 PERF_VSC_INPUT_TILES = 4,
763 };
764
765 enum a6xx_ccu_perfcounter_select {
766 PERF_CCU_BUSY_CYCLES = 0,
767 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
768 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
769 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
770 PERF_CCU_DEPTH_BLOCKS = 4,
771 PERF_CCU_COLOR_BLOCKS = 5,
772 PERF_CCU_DEPTH_BLOCK_HIT = 6,
773 PERF_CCU_COLOR_BLOCK_HIT = 7,
774 PERF_CCU_PARTIAL_BLOCK_READ = 8,
775 PERF_CCU_GMEM_READ = 9,
776 PERF_CCU_GMEM_WRITE = 10,
777 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
778 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
779 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
780 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
781 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
782 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
783 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
784 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
785 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
786 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
787 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
788 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
789 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
790 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
791 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
792 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
793 PERF_CCU_2D_RD_REQ = 27,
794 PERF_CCU_2D_WR_REQ = 28,
795 };
796
797 enum a6xx_lrz_perfcounter_select {
798 PERF_LRZ_BUSY_CYCLES = 0,
799 PERF_LRZ_STARVE_CYCLES_RAS = 1,
800 PERF_LRZ_STALL_CYCLES_RB = 2,
801 PERF_LRZ_STALL_CYCLES_VSC = 3,
802 PERF_LRZ_STALL_CYCLES_VPC = 4,
803 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
804 PERF_LRZ_STALL_CYCLES_UCHE = 6,
805 PERF_LRZ_LRZ_READ = 7,
806 PERF_LRZ_LRZ_WRITE = 8,
807 PERF_LRZ_READ_LATENCY = 9,
808 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
809 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
810 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
811 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
812 PERF_LRZ_FULL_8X8_TILES = 14,
813 PERF_LRZ_PARTIAL_8X8_TILES = 15,
814 PERF_LRZ_TILE_KILLED = 16,
815 PERF_LRZ_TOTAL_PIXEL = 17,
816 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
817 PERF_LRZ_FULLY_COVERED_TILES = 19,
818 PERF_LRZ_PARTIAL_COVERED_TILES = 20,
819 PERF_LRZ_FEEDBACK_ACCEPT = 21,
820 PERF_LRZ_FEEDBACK_DISCARD = 22,
821 PERF_LRZ_FEEDBACK_STALL = 23,
822 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
823 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
824 PERF_LRZ_STALL_CYCLES_VC = 26,
825 PERF_LRZ_RAS_MASK_TRANS = 27,
826 };
827
828 enum a6xx_cmp_perfcounter_select {
829 PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
830 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
831 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
832 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
833 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
834 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
835 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
836 PERF_CMPDECMP_VBIF_READ_DATA = 7,
837 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
838 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
839 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
840 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
841 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
842 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
843 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
844 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
845 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
846 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
847 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
848 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
849 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
850 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
851 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
852 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
853 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
854 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
855 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
856 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
857 PERF_CMPDECMP_2D_RD_DATA = 28,
858 PERF_CMPDECMP_2D_WR_DATA = 29,
859 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
860 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
861 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
862 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
863 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
864 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
865 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
866 PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
867 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
868 PERF_CMPDECMP_2D_PIXELS = 39,
869 };
870
871 enum a6xx_2d_ifmt {
872 R2D_UNORM8 = 16,
873 R2D_INT32 = 7,
874 R2D_INT16 = 6,
875 R2D_INT8 = 5,
876 R2D_FLOAT32 = 4,
877 R2D_FLOAT16 = 3,
878 R2D_UNORM8_SRGB = 1,
879 R2D_RAW = 0,
880 };
881
882 enum a6xx_ztest_mode {
883 A6XX_EARLY_Z = 0,
884 A6XX_LATE_Z = 1,
885 A6XX_EARLY_LRZ_LATE_Z = 2,
886 };
887
888 enum a6xx_rotation {
889 ROTATE_0 = 0,
890 ROTATE_90 = 1,
891 ROTATE_180 = 2,
892 ROTATE_270 = 3,
893 ROTATE_HFLIP = 4,
894 ROTATE_VFLIP = 5,
895 };
896
897 enum a6xx_tess_spacing {
898 TESS_EQUAL = 0,
899 TESS_FRACTIONAL_ODD = 2,
900 TESS_FRACTIONAL_EVEN = 3,
901 };
902
903 enum a6xx_tess_output {
904 TESS_POINTS = 0,
905 TESS_LINES = 1,
906 TESS_CW_TRIS = 2,
907 TESS_CCW_TRIS = 3,
908 };
909
910 enum a6xx_tex_filter {
911 A6XX_TEX_NEAREST = 0,
912 A6XX_TEX_LINEAR = 1,
913 A6XX_TEX_ANISO = 2,
914 A6XX_TEX_CUBIC = 3,
915 };
916
917 enum a6xx_tex_clamp {
918 A6XX_TEX_REPEAT = 0,
919 A6XX_TEX_CLAMP_TO_EDGE = 1,
920 A6XX_TEX_MIRROR_REPEAT = 2,
921 A6XX_TEX_CLAMP_TO_BORDER = 3,
922 A6XX_TEX_MIRROR_CLAMP = 4,
923 };
924
925 enum a6xx_tex_aniso {
926 A6XX_TEX_ANISO_1 = 0,
927 A6XX_TEX_ANISO_2 = 1,
928 A6XX_TEX_ANISO_4 = 2,
929 A6XX_TEX_ANISO_8 = 3,
930 A6XX_TEX_ANISO_16 = 4,
931 };
932
933 enum a6xx_reduction_mode {
934 A6XX_REDUCTION_MODE_AVERAGE = 0,
935 A6XX_REDUCTION_MODE_MIN = 1,
936 A6XX_REDUCTION_MODE_MAX = 2,
937 };
938
939 enum a6xx_tex_swiz {
940 A6XX_TEX_X = 0,
941 A6XX_TEX_Y = 1,
942 A6XX_TEX_Z = 2,
943 A6XX_TEX_W = 3,
944 A6XX_TEX_ZERO = 4,
945 A6XX_TEX_ONE = 5,
946 };
947
948 enum a6xx_tex_type {
949 A6XX_TEX_1D = 0,
950 A6XX_TEX_2D = 1,
951 A6XX_TEX_CUBE = 2,
952 A6XX_TEX_3D = 3,
953 };
954
955 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
956 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
957 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
958 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
959 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
960 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
961 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
962 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
963 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
964 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
965 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
966 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
967 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
968 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
969 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
970 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
971 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
972 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
973 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
974 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
975 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
976 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
977 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
978 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
979 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
980 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
981 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
982 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
983 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
984 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
985 #define REG_A6XX_CP_RB_BASE 0x00000800
986
987 #define REG_A6XX_CP_RB_BASE_HI 0x00000801
988
989 #define REG_A6XX_CP_RB_CNTL 0x00000802
990
991 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
992
993 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
994
995 #define REG_A6XX_CP_RB_RPTR 0x00000806
996
997 #define REG_A6XX_CP_RB_WPTR 0x00000807
998
999 #define REG_A6XX_CP_SQE_CNTL 0x00000808
1000
1001 #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
1002 #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1003
1004 #define REG_A6XX_CP_HW_FAULT 0x00000821
1005
1006 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1007
1008 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1009
1010 #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
1011
1012 #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1013
1014 #define REG_A6XX_CP_MISC_CNTL 0x00000840
1015
1016 #define REG_A6XX_CP_APRIV_CNTL 0x00000844
1017
1018 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1019 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
1020 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)1021 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
1022 {
1023 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
1024 }
1025 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00
1026 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8
A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)1027 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
1028 {
1029 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
1030 }
1031 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
1032 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)1033 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1034 {
1035 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1036 }
1037 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
1038 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)1039 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1040 {
1041 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1042 }
1043
1044 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
1045 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
1046 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)1047 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1048 {
1049 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1050 }
1051 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
1052 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)1053 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1054 {
1055 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1056 }
1057
1058 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
1059
1060 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841
1061
1062 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
1063
1064 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
1065
1066 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
1067
REG_A6XX_CP_SCRATCH(uint32_t i0)1068 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1069
REG_A6XX_CP_SCRATCH_REG(uint32_t i0)1070 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1071
REG_A6XX_CP_PROTECT(uint32_t i0)1072 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1073
REG_A6XX_CP_PROTECT_REG(uint32_t i0)1074 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1075 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
1076 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)1077 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1078 {
1079 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1080 }
1081 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
1082 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)1083 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1084 {
1085 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1086 }
1087 #define A6XX_CP_PROTECT_REG_READ 0x80000000
1088
1089 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
1090
1091 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
1092
1093 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
1094
1095 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
1096
1097 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
1098
1099 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1100
1101 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1102
1103 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1104
1105 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1106
1107 #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
1108
1109 #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1110
1111 #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1112
1113 #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1114
1115 #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1116
1117 #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1118
1119 #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1120
1121 #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1122
1123 #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1124
1125 #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1126
1127 #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1128
1129 #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1130
1131 #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1132
1133 #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1134
1135 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1136
1137 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1138
1139 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1140
1141 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1142
1143 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
1144
1145 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
1146
1147 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
1148
1149 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
1150
1151 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
1152
1153 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
1154
1155 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
1156
1157 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
1158
1159 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
1160
1161 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
1162
1163 #define REG_A6XX_CP_IB1_BASE 0x00000928
1164
1165 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929
1166
1167 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
1168
1169 #define REG_A6XX_CP_IB2_BASE 0x0000092b
1170
1171 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1172
1173 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1174
1175 #define REG_A6XX_CP_SDS_BASE 0x0000092e
1176
1177 #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1178
1179 #define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e
1180
1181 #define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931
1182
1183 #define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932
1184
1185 #define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934
1186
1187 #define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935
1188
1189 #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1190 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
1191 #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)1192 static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1193 {
1194 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1195 }
1196
1197 #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
1198 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
1199 #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)1200 static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1201 {
1202 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1203 }
1204
1205 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1206
1207 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1208
1209 #define REG_A6XX_CP_AHB_CNTL 0x0000098d
1210
1211 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1212
1213 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1214
1215 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1216
1217 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1218
1219 #define REG_A6XX_RBBM_STATUS 0x00000210
1220 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1221 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1222 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
1223 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
1224 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
1225 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
1226 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
1227 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
1228 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
1229 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
1230 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
1231 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
1232 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
1233 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
1234 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
1235 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
1236 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
1237 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
1238 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
1239 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
1240 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
1241 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
1242 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1243 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1244
1245 #define REG_A6XX_RBBM_STATUS3 0x00000213
1246 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1247
1248 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1249
1250 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
1251
1252 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1253
1254 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1255
1256 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1257
1258 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1259
1260 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1261
1262 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1263
1264 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1265
1266 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1267
1268 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1269
1270 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1271
1272 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1273
1274 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1275
1276 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1277
1278 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1279
1280 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1281
1282 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1283
1284 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1285
1286 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1287
1288 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1289
1290 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1291
1292 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1293
1294 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1295
1296 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1297
1298 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1299
1300 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1301
1302 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1303
1304 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1305
1306 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1307
1308 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1309
1310 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1311
1312 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1313
1314 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1315
1316 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1317
1318 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1319
1320 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1321
1322 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1323
1324 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1325
1326 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1327
1328 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1329
1330 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1331
1332 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1333
1334 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1335
1336 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1337
1338 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1339
1340 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1341
1342 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1343
1344 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1345
1346 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1347
1348 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1349
1350 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1351
1352 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1353
1354 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1355
1356 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1357
1358 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1359
1360 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1361
1362 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1363
1364 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1365
1366 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1367
1368 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1369
1370 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1371
1372 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1373
1374 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1375
1376 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1377
1378 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1379
1380 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1381
1382 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1383
1384 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1385
1386 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1387
1388 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1389
1390 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1391
1392 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1393
1394 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1395
1396 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1397
1398 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1399
1400 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1401
1402 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1403
1404 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1405
1406 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1407
1408 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1409
1410 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1411
1412 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1413
1414 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1415
1416 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1417
1418 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1419
1420 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1421
1422 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1423
1424 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1425
1426 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1427
1428 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1429
1430 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1431
1432 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1433
1434 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1435
1436 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1437
1438 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1439
1440 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1441
1442 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1443
1444 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1445
1446 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1447
1448 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1449
1450 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1451
1452 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1453
1454 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1455
1456 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1457
1458 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1459
1460 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1461
1462 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1463
1464 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1465
1466 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1467
1468 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1469
1470 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1471
1472 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1473
1474 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1475
1476 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1477
1478 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1479
1480 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1481
1482 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1483
1484 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1485
1486 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1487
1488 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1489
1490 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1491
1492 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1493
1494 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1495
1496 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1497
1498 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1499
1500 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1501
1502 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1503
1504 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1505
1506 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1507
1508 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1509
1510 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1511
1512 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1513
1514 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1515
1516 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1517
1518 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1519
1520 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1521
1522 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1523
1524 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1525
1526 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1527
1528 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1529
1530 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1531
1532 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1533
1534 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1535
1536 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1537
1538 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1539
1540 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1541
1542 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1543
1544 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1545
1546 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1547
1548 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1549
1550 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1551
1552 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1553
1554 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1555
1556 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1557
1558 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1559
1560 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1561
1562 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1563
1564 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1565
1566 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1567
1568 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1569
1570 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
1571
1572 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
1573
1574 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
1575
1576 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
1577
1578 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
1579
1580 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
1581
1582 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
1583
1584 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
1585
1586 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
1587
1588 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
1589
1590 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
1591
1592 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
1593
1594 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
1595
1596 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
1597
1598 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
1599
1600 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1601
1602 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1603
1604 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1605
1606 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1607
1608 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1609
1610 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1611
1612 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1613
1614 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1615
1616 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1617
1618 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1619
1620 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1621
1622 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1623
1624 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1625
1626 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1627
1628 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1629
1630 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1631
1632 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1633
1634 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1635
1636 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1637
1638 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1639
1640 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1641
1642 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1643
1644 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1645
1646 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1647
1648 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1649
1650 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1651
1652 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1653
1654 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1655
1656 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1657
1658 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1659
1660 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1661
1662 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1663
1664 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1665
1666 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1667
1668 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1669
1670 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1671
1672 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1673
1674 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1675
1676 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1677
1678 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1679
1680 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1681
1682 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1683
1684 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1685
1686 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1687
1688 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1689
1690 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1691
1692 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1693
1694 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1695
1696 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1697
1698 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1699
1700 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1701
1702 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1703
1704 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1705
1706 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1707
1708 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1709
1710 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1711
1712 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1713
1714 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1715
1716 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1717
1718 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1719
1720 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1721
1722 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1723
1724 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1725
1726 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1727
1728 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1729
1730 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1731
1732 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1733
1734 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1735
1736 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1737
1738 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1739
1740 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1741
1742 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1743
1744 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1745
1746 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1747
1748 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1749
1750 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1751
1752 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1753
1754 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1755
1756 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1757
1758 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1759
1760 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1761
1762 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1763
1764 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1765
1766 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1767
1768 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1769
1770 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1771
1772 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1773
1774 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1775
1776 #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1777
1778 #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1779
1780 #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
1781
1782 #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
1783
1784 #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
1785
1786 #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
1787
1788 #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
1789
1790 #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
1791
1792 #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
1793
1794 #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
1795
1796 #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
1797
1798 #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
1799
1800 #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
1801
1802 #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
1803
1804 #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
1805
1806 #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
1807
1808 #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
1809
1810 #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
1811
1812 #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
1813
1814 #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
1815
1816 #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
1817
1818 #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
1819
1820 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1821
1822 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1823
1824 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1825
1826 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1827
1828 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1829
1830 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1831
1832 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1833
1834 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
1835
1836 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
1837 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
1838
1839 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1840
1841 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1842
1843 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1844
1845 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1846
1847 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1848
1849 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1850
1851 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1852
1853 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1854
1855 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1856
1857 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1858
1859 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1860
1861 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1862
1863 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1864
1865 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1866
1867 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1868
1869 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1870
1871 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1872
1873 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1874
1875 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1876
1877 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1878
1879 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1880
1881 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1882
1883 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1884
1885 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1886
1887 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1888
1889 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1890
1891 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1892
1893 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1894
1895 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1896
1897 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1898
1899 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1900
1901 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1902
1903 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1904
1905 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1906
1907 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1908
1909 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1910
1911 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1912
1913 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1914
1915 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1916
1917 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1918
1919 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1920
1921 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1922
1923 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1924
1925 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1926
1927 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1928
1929 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1930
1931 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1932
1933 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1934
1935 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1936
1937 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1938
1939 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1940
1941 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1942
1943 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1944
1945 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1946
1947 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1948
1949 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1950
1951 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1952
1953 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1954
1955 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1956
1957 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1958
1959 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1960
1961 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1962
1963 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1964
1965 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1966
1967 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1968
1969 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1970
1971 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1972
1973 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1974
1975 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1976
1977 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1978
1979 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1980
1981 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1982
1983 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1984
1985 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1986
1987 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1988
1989 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1990
1991 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1992
1993 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1994
1995 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1996
1997 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1998
1999 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
2000
2001 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
2002
2003 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
2004
2005 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
2006
2007 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
2008
2009 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
2010
2011 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
2012
2013 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
2014
2015 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
2016
2017 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
2018
2019 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
2020
2021 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
2022
2023 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
2024
2025 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
2026
2027 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
2028
2029 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
2030
2031 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
2032
2033 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
2034
2035 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
2036
2037 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
2038
2039 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
2040
2041 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
2042
2043 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
2044
2045 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
2046
2047 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
2048
2049 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
2050
2051 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
2052
2053 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
2054
2055 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
2056
2057 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
2058
2059 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
2060
2061 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
2062
2063 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
2064
2065 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
2066
2067 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
2068
2069 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
2070
2071 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
2072
2073 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
2074
2075 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
2076
2077 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
2078
2079 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
2080
2081 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
2082 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
2083 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)2084 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
2085 {
2086 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
2087 }
2088 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
2089 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)2090 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
2091 {
2092 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
2093 }
2094
2095 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
2096 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
2097 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)2098 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
2099 {
2100 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
2101 }
2102 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
2103 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)2104 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
2105 {
2106 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
2107 }
2108 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
2109 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)2110 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
2111 {
2112 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
2113 }
2114
2115 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
2116 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
2117 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)2118 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
2119 {
2120 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
2121 }
2122
2123 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
2124
2125 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
2126
2127 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
2128
2129 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
2130
2131 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
2132
2133 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
2134
2135 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
2136
2137 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
2138
2139 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
2140 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
2141 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)2142 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
2143 {
2144 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
2145 }
2146 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
2147 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)2148 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
2149 {
2150 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
2151 }
2152 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
2153 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)2154 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
2155 {
2156 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
2157 }
2158 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
2159 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)2160 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
2161 {
2162 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
2163 }
2164 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
2165 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)2166 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
2167 {
2168 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
2169 }
2170 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
2171 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)2172 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
2173 {
2174 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
2175 }
2176 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
2177 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)2178 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
2179 {
2180 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
2181 }
2182 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
2183 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)2184 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
2185 {
2186 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
2187 }
2188
2189 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
2190 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
2191 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)2192 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
2193 {
2194 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
2195 }
2196 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
2197 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)2198 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
2199 {
2200 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
2201 }
2202 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
2203 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)2204 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
2205 {
2206 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
2207 }
2208 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
2209 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)2210 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
2211 {
2212 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
2213 }
2214 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
2215 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)2216 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
2217 {
2218 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
2219 }
2220 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
2221 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)2222 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
2223 {
2224 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
2225 }
2226 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
2227 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)2228 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
2229 {
2230 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
2231 }
2232 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
2233 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)2234 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2235 {
2236 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2237 }
2238
2239 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2240
2241 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2242
2243 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
2244
2245 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
2246
2247 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
2248
2249 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
2250
2251 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
2252
2253 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
2254
2255 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
2256
2257 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
2258
2259 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2260
2261 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2262
2263 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2264
2265 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
2266
2267 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
2268
2269 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
2270
2271 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
2272
2273 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
2274
2275 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
2276
2277 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
2278
2279 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
2280
2281 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
2282
2283 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2284
2285 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2286
2287 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2288
2289 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2290
2291 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
2292
2293 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
2294
2295 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
2296
2297 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
2298
2299 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
2300
2301 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
2302
2303 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
2304
2305 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
2306
2307 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2308
2309 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2310
2311 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2312 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2313 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)2314 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2315 {
2316 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2317 }
2318
2319 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
2320
2321 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
2322
2323 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
2324
2325 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
2326
2327 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
2328
2329 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
2330
2331 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
2332
2333 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
2334
2335 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
2336
2337 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
2338
2339 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
2340
2341 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
2342
2343 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
2344
2345 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
2346
2347 #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
2348
2349 #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
2350
2351 #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
2352
2353 #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
2354
2355 #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
2356
2357 #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
2358
2359 #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
2360
2361 #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
2362
2363 #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
2364
2365 #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
2366
2367 #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
2368
2369 #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
2370
2371 #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
2372
2373 #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
2374
2375 #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
2376
2377 #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
2378
2379 #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
2380
2381 #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
2382
2383 #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
2384
2385 #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
2386
2387 #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
2388
2389 #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
2390
2391 #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
2392
2393 #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
2394
2395 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
2396
2397 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
2398
2399 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
2400
2401 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
2402
2403 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
2404
2405 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
2406
2407 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
2408
2409 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
2410
2411 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
2412
2413 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
2414
2415 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
2416
2417 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
2418
2419 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
2420
2421 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
2422
2423 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
2424
2425 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
2426
2427 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
2428
2429 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
2430
2431 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
2432
2433 #define REG_A6XX_VBIF_VERSION 0x00003000
2434
2435 #define REG_A6XX_VBIF_CLKON 0x00003001
2436 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
2437
2438 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2439
2440 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
2441
2442 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
2443
2444 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2445
2446 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2447
2448 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2449 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
2450 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)2451 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2452 {
2453 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2454 }
2455
2456 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2457
2458 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2459 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
2460 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)2461 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2462 {
2463 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2464 }
2465
2466 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
2467
2468 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
2469
2470 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
2471
2472 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
2473
2474 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
2475
2476 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
2477
2478 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
2479
2480 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
2481
2482 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
2483
2484 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2485
2486 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2487
2488 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2489
2490 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2491
2492 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2493
2494 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2495
2496 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2497
2498 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2499
2500 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2501
2502 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2503
2504 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2505
2506 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2507
2508 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2509
2510 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
2511
2512 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
2513
2514 #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
2515
2516 #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
2517
2518 #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
2519
2520 #define REG_A6XX_GBIF_HALT 0x00003c45
2521
2522 #define REG_A6XX_GBIF_HALT_ACK 0x00003c46
2523
2524 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
2525
2526 #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
2527
2528 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
2529
2530 #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
2531
2532 #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
2533
2534 #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
2535
2536 #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
2537
2538 #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
2539
2540 #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
2541
2542 #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
2543
2544 #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
2545
2546 #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
2547
2548 #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
2549
2550 #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
2551
2552 #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
2553
2554 #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
2555
2556 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
2557
2558 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
2559 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2560 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
2561 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_WINDOW_OFFSET_X(uint32_t val)2562 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2563 {
2564 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2565 }
2566 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2567 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)2568 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2569 {
2570 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2571 }
2572
2573 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
2574 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2575 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
2576 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)2577 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2578 {
2579 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2580 }
2581 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2582 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)2583 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2584 {
2585 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2586 }
2587
2588 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2589 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2590 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)2591 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2592 {
2593 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2594 }
2595 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2596 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)2597 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2598 {
2599 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2600 }
2601
2602 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
2603
2604 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
2605
2606 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
2607
2608 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2609 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2610 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
A6XX_VSC_BIN_COUNT_NX(uint32_t val)2611 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2612 {
2613 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2614 }
2615 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
2616 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
A6XX_VSC_BIN_COUNT_NY(uint32_t val)2617 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2618 {
2619 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2620 }
2621
REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0)2622 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2623
REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0)2624 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2625 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2626 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)2627 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2628 {
2629 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2630 }
2631 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2632 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)2633 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2634 {
2635 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2636 }
2637 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
2638 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)2639 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2640 {
2641 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2642 }
2643 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2644 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)2645 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2646 {
2647 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2648 }
2649
2650 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
2651
2652 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
2653
2654 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2655
2656 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2657
2658 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2659
2660 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
2661
2662 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
2663
2664 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2665
2666 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2667
2668 #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2669
REG_A6XX_VSC_STATE(uint32_t i0)2670 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2671
REG_A6XX_VSC_STATE_REG(uint32_t i0)2672 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2673
REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0)2674 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2675
REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0)2676 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2677
REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0)2678 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2679
REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0)2680 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2681
2682 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2683
2684 #define REG_A6XX_GRAS_CL_CNTL 0x00008000
2685 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
2686 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
2687 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
2688 #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020
2689 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2690 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
2691 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
2692 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
2693
2694 #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
2695 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2696 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)2697 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2698 {
2699 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2700 }
2701 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2702 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)2703 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2704 {
2705 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2706 }
2707
2708 #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
2709 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2710 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)2711 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2712 {
2713 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2714 }
2715 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2716 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)2717 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2718 {
2719 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2720 }
2721
2722 #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
2723 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2724 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)2725 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2726 {
2727 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2728 }
2729 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2730 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)2731 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2732 {
2733 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2734 }
2735
2736 #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
2737
2738 #define REG_A6XX_GRAS_CNTL 0x00008005
2739 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2740 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2741 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2742 #define A6XX_GRAS_CNTL_SIZE 0x00000008
2743 #define A6XX_GRAS_CNTL_UNK4 0x00000010
2744 #define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
2745 #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2746 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)2747 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2748 {
2749 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2750 }
2751
2752 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2753 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
2754 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)2755 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2756 {
2757 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2758 }
2759 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
2760 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)2761 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2762 {
2763 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2764 }
2765
REG_A6XX_GRAS_CL_VPORT(uint32_t i0)2766 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2767
REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0)2768 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2769 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
2770 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_XOFFSET(float val)2771 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
2772 {
2773 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
2774 }
2775
REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0)2776 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2777 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
2778 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_XSCALE(float val)2779 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
2780 {
2781 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
2782 }
2783
REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0)2784 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2785 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
2786 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_YOFFSET(float val)2787 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
2788 {
2789 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
2790 }
2791
REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0)2792 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2793 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
2794 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_YSCALE(float val)2795 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
2796 {
2797 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
2798 }
2799
REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0)2800 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2801 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
2802 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_ZOFFSET(float val)2803 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
2804 {
2805 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
2806 }
2807
REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0)2808 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2809 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
2810 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_ZSCALE(float val)2811 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
2812 {
2813 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2814 }
2815
REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0)2816 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2817
REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0)2818 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2819 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
2820 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MIN(float val)2821 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2822 {
2823 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2824 }
2825
REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0)2826 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2827 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
2828 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MAX(float val)2829 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2830 {
2831 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
2832 }
2833
2834 #define REG_A6XX_GRAS_SU_CNTL 0x00008090
2835 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2836 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2837 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2838 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2839 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)2840 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2841 {
2842 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2843 }
2844 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2845 #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2846 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)2847 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2848 {
2849 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2850 }
2851 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2852 #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000
2853 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)2854 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2855 {
2856 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2857 }
2858
2859 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2860 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2861 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)2862 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2863 {
2864 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2865 }
2866 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2867 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)2868 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2869 {
2870 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2871 }
2872
2873 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2874 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
2875 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
A6XX_GRAS_SU_POINT_SIZE(float val)2876 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2877 {
2878 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2879 }
2880
2881 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
2882 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
2883 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)2884 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2885 {
2886 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
2887 }
2888
2889 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2890 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2891 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)2892 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2893 {
2894 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2895 }
2896
2897 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2898 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2899 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)2900 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2901 {
2902 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2903 }
2904
2905 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2906 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2907 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)2908 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2909 {
2910 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2911 }
2912
2913 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2914 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2915 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)2916 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2917 {
2918 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2919 }
2920 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
2921 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)2922 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2923 {
2924 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2925 }
2926
2927 #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
2928
2929 #define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a
2930
2931 #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
2932 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
2933 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
2934
2935 #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
2936 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
2937 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
2938
2939 #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
2940 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
2941 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
2942
2943 #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
2944
2945 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
2946 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
2947 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)2948 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2949 {
2950 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2951 }
2952 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
2953 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)2954 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2955 {
2956 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2957 }
2958 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
2959 #define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000
2960 #define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19
A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)2961 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
2962 {
2963 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
2964 }
2965 #define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000
2966 #define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20
A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)2967 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
2968 {
2969 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
2970 }
2971 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
2972 #define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000
2973 #define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22
A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)2974 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
2975 {
2976 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
2977 }
2978
2979 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2980 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2981 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2982 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2983 {
2984 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2985 }
2986 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2987 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)2988 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2989 {
2990 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2991 }
2992 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2993 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)2994 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2995 {
2996 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
2997 }
2998
2999 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
3000 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3001 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3002 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3003 {
3004 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
3005 }
3006 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3007
3008 #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
3009 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
3010 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
3011
3012 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
3013 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
3014 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)3015 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
3016 {
3017 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3018 }
3019 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
3020 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)3021 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3022 {
3023 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3024 }
3025 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
3026 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)3027 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3028 {
3029 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3030 }
3031 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
3032 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)3033 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3034 {
3035 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3036 }
3037 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
3038 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)3039 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3040 {
3041 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3042 }
3043 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
3044 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)3045 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3046 {
3047 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3048 }
3049 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
3050 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)3051 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3052 {
3053 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3054 }
3055 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
3056 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)3057 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3058 {
3059 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3060 }
3061
3062 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
3063 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
3064 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)3065 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3066 {
3067 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3068 }
3069 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
3070 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)3071 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3072 {
3073 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3074 }
3075 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
3076 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)3077 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3078 {
3079 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3080 }
3081 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
3082 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)3083 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3084 {
3085 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3086 }
3087 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
3088 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)3089 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3090 {
3091 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3092 }
3093 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
3094 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)3095 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3096 {
3097 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3098 }
3099 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
3100 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)3101 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3102 {
3103 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3104 }
3105 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
3106 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)3107 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3108 {
3109 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3110 }
3111
3112 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
3113
REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0)3114 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
3115
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0)3116 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
3117 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
3118 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)3119 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3120 {
3121 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3122 }
3123 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
3124 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)3125 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3126 {
3127 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3128 }
3129
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0)3130 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
3131 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
3132 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)3133 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3134 {
3135 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3136 }
3137 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
3138 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)3139 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3140 {
3141 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3142 }
3143
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0)3144 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
3145
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0)3146 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
3147 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
3148 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)3149 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
3150 {
3151 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
3152 }
3153 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
3154 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)3155 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
3156 {
3157 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
3158 }
3159
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0)3160 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
3161 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
3162 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)3163 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
3164 {
3165 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
3166 }
3167 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
3168 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)3169 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
3170 {
3171 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
3172 }
3173
3174 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
3175 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
3176 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)3177 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3178 {
3179 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3180 }
3181 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
3182 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)3183 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3184 {
3185 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3186 }
3187
3188 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
3189 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
3190 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)3191 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3192 {
3193 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3194 }
3195 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
3196 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)3197 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3198 {
3199 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3200 }
3201
3202 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
3203 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
3204 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
3205 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
3206 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
3207 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
3208 #define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0
3209 #define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5
A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)3210 static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
3211 {
3212 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
3213 }
3214
3215 #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
3216
3217 #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
3218 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
3219 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)3220 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
3221 {
3222 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
3223 }
3224
3225 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
3226
3227 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
3228
3229 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
3230 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
3231 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)3232 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
3233 {
3234 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
3235 }
3236
3237 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
3238 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
3239 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)3240 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
3241 {
3242 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
3243 }
3244 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
3245 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)3246 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3247 {
3248 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3249 }
3250
3251 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
3252
3253 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
3254
3255 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
3256 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
3257 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)3258 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
3259 {
3260 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
3261 }
3262
3263 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
3264 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3265
3266 #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a
3267 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff
3268 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0
A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)3269 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
3270 {
3271 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
3272 }
3273 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000
3274 #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16
A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)3275 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
3276 {
3277 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
3278 }
3279 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000
3280 #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28
A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)3281 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
3282 {
3283 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
3284 }
3285
3286 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
3287
3288 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
3289 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
3290 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)3291 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3292 {
3293 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
3294 }
3295 #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078
3296 #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3
A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)3297 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
3298 {
3299 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
3300 }
3301 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
3302 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3303 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)3304 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
3305 {
3306 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3307 }
3308 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
3309 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
3310 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)3311 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
3312 {
3313 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
3314 }
3315 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
3316 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
3317 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)3318 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
3319 {
3320 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
3321 }
3322 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
3323 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)3324 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3325 {
3326 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
3327 }
3328 #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000
3329 #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29
A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)3330 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
3331 {
3332 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
3333 }
3334
3335 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
3336
3337 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
3338
3339 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
3340
3341 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
3342
3343 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405
3344 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
3345 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
A6XX_GRAS_2D_DST_TL_X(uint32_t val)3346 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
3347 {
3348 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
3349 }
3350 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
3351 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
A6XX_GRAS_2D_DST_TL_Y(uint32_t val)3352 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
3353 {
3354 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
3355 }
3356
3357 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406
3358 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
3359 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
A6XX_GRAS_2D_DST_BR_X(uint32_t val)3360 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
3361 {
3362 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
3363 }
3364 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
3365 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
A6XX_GRAS_2D_DST_BR_Y(uint32_t val)3366 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
3367 {
3368 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
3369 }
3370
3371 #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
3372
3373 #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
3374
3375 #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
3376
3377 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
3378 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
3379 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)3380 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
3381 {
3382 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
3383 }
3384 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
3385 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)3386 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
3387 {
3388 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
3389 }
3390
3391 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
3392 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
3393 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)3394 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
3395 {
3396 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
3397 }
3398 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
3399 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)3400 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
3401 {
3402 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
3403 }
3404
3405 #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
3406
3407 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
3408
3409 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
3410
3411 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
3412
3413 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
3414
3415 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
3416
3417 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
3418
3419 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
3420
3421 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
3422
3423 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
3424
3425 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
3426
3427 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
3428
3429 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
3430
3431 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
3432
3433 #define REG_A6XX_RB_BIN_CONTROL 0x00008800
3434 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
3435 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL_BINW(uint32_t val)3436 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3437 {
3438 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3439 }
3440 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
3441 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL_BINH(uint32_t val)3442 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3443 {
3444 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3445 }
3446 #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
3447 #define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000
3448 #define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19
A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)3449 static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
3450 {
3451 return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
3452 }
3453 #define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000
3454 #define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20
A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)3455 static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
3456 {
3457 return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
3458 }
3459 #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
3460 #define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000
3461 #define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22
A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)3462 static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
3463 {
3464 return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
3465 }
3466
3467 #define REG_A6XX_RB_RENDER_CNTL 0x00008801
3468 #define A6XX_RB_RENDER_CNTL_UNK3 0x00000008
3469 #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
3470 #define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060
3471 #define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5
A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)3472 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
3473 {
3474 return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
3475 }
3476 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
3477 #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00
3478 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)3479 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
3480 {
3481 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
3482 }
3483 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
3484 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
3485 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)3486 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3487 {
3488 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3489 }
3490
3491 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
3492 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3493 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3494 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3495 {
3496 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3497 }
3498 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
3499 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)3500 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
3501 {
3502 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
3503 }
3504 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
3505 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)3506 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
3507 {
3508 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
3509 }
3510
3511 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
3512 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3513 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3514 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3515 {
3516 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3517 }
3518 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3519
3520 #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
3521 #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
3522 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
3523
3524 #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
3525 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
3526 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)3527 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
3528 {
3529 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3530 }
3531 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
3532 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)3533 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3534 {
3535 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3536 }
3537 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
3538 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)3539 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3540 {
3541 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3542 }
3543 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
3544 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)3545 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3546 {
3547 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3548 }
3549 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
3550 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)3551 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3552 {
3553 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3554 }
3555 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
3556 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)3557 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3558 {
3559 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3560 }
3561 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
3562 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)3563 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3564 {
3565 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3566 }
3567 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
3568 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)3569 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3570 {
3571 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3572 }
3573
3574 #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
3575 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
3576 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)3577 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3578 {
3579 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3580 }
3581 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
3582 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)3583 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3584 {
3585 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3586 }
3587 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
3588 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)3589 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3590 {
3591 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3592 }
3593 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
3594 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)3595 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3596 {
3597 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3598 }
3599 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
3600 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)3601 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3602 {
3603 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3604 }
3605 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
3606 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)3607 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3608 {
3609 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3610 }
3611 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
3612 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)3613 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3614 {
3615 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3616 }
3617 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
3618 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)3619 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3620 {
3621 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3622 }
3623
3624 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
3625 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3626 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3627 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3628 #define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
3629 #define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010
3630 #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
3631 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3632 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)3633 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3634 {
3635 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3636 }
3637 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
3638
3639 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
3640 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3641 #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002
3642 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
3643 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
3644 #define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
3645 #define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
3646 #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
3647 #define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080
3648 #define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100
3649
3650 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
3651 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
3652 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
3653 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
3654 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
3655
3656 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
3657 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
3658 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)3659 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3660 {
3661 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3662 }
3663
3664 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
3665 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3666 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)3667 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3668 {
3669 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3670 }
3671 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3672 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)3673 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3674 {
3675 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3676 }
3677 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3678 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)3679 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3680 {
3681 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3682 }
3683 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3684 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)3685 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3686 {
3687 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3688 }
3689 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3690 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)3691 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3692 {
3693 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3694 }
3695 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3696 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)3697 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3698 {
3699 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3700 }
3701 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3702 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)3703 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3704 {
3705 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3706 }
3707 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3708 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)3709 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3710 {
3711 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3712 }
3713
3714 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e
3715 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
3716 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)3717 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3718 {
3719 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3720 }
3721 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
3722 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)3723 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3724 {
3725 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3726 }
3727 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
3728 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)3729 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3730 {
3731 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3732 }
3733 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
3734 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)3735 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3736 {
3737 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3738 }
3739 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
3740 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)3741 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3742 {
3743 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3744 }
3745 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
3746 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)3747 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3748 {
3749 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3750 }
3751 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
3752 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)3753 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3754 {
3755 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3756 }
3757 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
3758 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)3759 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3760 {
3761 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3762 }
3763
3764 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f
3765 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
3766 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
3767 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
3768 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
3769 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
3770 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
3771 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
3772 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
3773
3774 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
3775 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3776
3777 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811
3778
3779 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818
3780
3781 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819
3782
3783 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
3784
3785 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
3786
3787 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
3788
3789 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
3790
3791 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
3792
REG_A6XX_RB_MRT(uint32_t i0)3793 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3794
REG_A6XX_RB_MRT_CONTROL(uint32_t i0)3795 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3796 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
3797 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
3798 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3799 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3800 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)3801 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3802 {
3803 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3804 }
3805 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3806 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)3807 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3808 {
3809 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3810 }
3811
REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0)3812 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3813 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3814 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)3815 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3816 {
3817 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3818 }
3819 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3820 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3821 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3822 {
3823 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3824 }
3825 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3826 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)3827 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3828 {
3829 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3830 }
3831 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3832 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)3833 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3834 {
3835 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3836 }
3837 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3838 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3839 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3840 {
3841 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3842 }
3843 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3844 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)3845 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3846 {
3847 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3848 }
3849
REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0)3850 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3851 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3852 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)3853 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
3854 {
3855 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3856 }
3857 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3858 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)3859 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3860 {
3861 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3862 }
3863 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400
3864 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10
A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)3865 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3866 {
3867 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3868 }
3869 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3870 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)3871 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3872 {
3873 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3874 }
3875
REG_A6XX_RB_MRT_PITCH(uint32_t i0)3876 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3877 #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff
3878 #define A6XX_RB_MRT_PITCH__SHIFT 0
A6XX_RB_MRT_PITCH(uint32_t val)3879 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3880 {
3881 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3882 }
3883
REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0)3884 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3885 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3886 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)3887 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3888 {
3889 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3890 }
3891
REG_A6XX_RB_MRT_BASE_LO(uint32_t i0)3892 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3893
REG_A6XX_RB_MRT_BASE_HI(uint32_t i0)3894 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3895
REG_A6XX_RB_MRT_BASE(uint32_t i0)3896 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3897 #define A6XX_RB_MRT_BASE__MASK 0xffffffff
3898 #define A6XX_RB_MRT_BASE__SHIFT 0
A6XX_RB_MRT_BASE(uint32_t val)3899 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3900 {
3901 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3902 }
3903
REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0)3904 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3905 #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000
3906 #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12
A6XX_RB_MRT_BASE_GMEM(uint32_t val)3907 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3908 {
3909 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3910 }
3911
3912 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
3913 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
3914 #define A6XX_RB_BLEND_RED_F32__SHIFT 0
A6XX_RB_BLEND_RED_F32(float val)3915 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3916 {
3917 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3918 }
3919
3920 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
3921 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3922 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
A6XX_RB_BLEND_GREEN_F32(float val)3923 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3924 {
3925 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3926 }
3927
3928 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
3929 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3930 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
A6XX_RB_BLEND_BLUE_F32(float val)3931 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3932 {
3933 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3934 }
3935
3936 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
3937 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3938 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
A6XX_RB_BLEND_ALPHA_F32(float val)3939 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3940 {
3941 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3942 }
3943
3944 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
3945 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3946 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)3947 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3948 {
3949 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3950 }
3951 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3952 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3953 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)3954 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3955 {
3956 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3957 }
3958
3959 #define REG_A6XX_RB_BLEND_CNTL 0x00008865
3960 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3961 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)3962 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3963 {
3964 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3965 }
3966 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3967 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
3968 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3969 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
3970 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3971 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)3972 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3973 {
3974 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3975 }
3976
3977 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
3978 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
3979 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)3980 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3981 {
3982 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
3983 }
3984
3985 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
3986 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3987 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3988 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3989 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)3990 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3991 {
3992 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3993 }
3994 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
3995 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3996 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
3997
3998 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
3999 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
4000 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)4001 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
4002 {
4003 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
4004 }
4005 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
4006 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)4007 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
4008 {
4009 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
4010 }
4011
4012 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
4013 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
4014 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)4015 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
4016 {
4017 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
4018 }
4019
4020 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
4021 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
4022 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)4023 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
4024 {
4025 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
4026 }
4027
4028 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
4029
4030 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
4031
4032 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
4033 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
4034 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)4035 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
4036 {
4037 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
4038 }
4039
4040 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
4041 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000
4042 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)4043 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
4044 {
4045 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
4046 }
4047
4048 #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
4049 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
4050 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
A6XX_RB_Z_BOUNDS_MIN(float val)4051 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
4052 {
4053 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
4054 }
4055
4056 #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
4057 #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
4058 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
A6XX_RB_Z_BOUNDS_MAX(float val)4059 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
4060 {
4061 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
4062 }
4063
4064 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
4065 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
4066 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
4067 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
4068 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
4069 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)4070 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
4071 {
4072 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
4073 }
4074 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
4075 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)4076 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
4077 {
4078 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
4079 }
4080 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
4081 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)4082 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
4083 {
4084 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
4085 }
4086 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
4087 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)4088 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
4089 {
4090 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
4091 }
4092 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
4093 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)4094 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
4095 {
4096 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
4097 }
4098 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
4099 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)4100 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
4101 {
4102 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
4103 }
4104 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
4105 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)4106 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
4107 {
4108 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
4109 }
4110 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
4111 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)4112 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
4113 {
4114 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
4115 }
4116
4117 #define REG_A6XX_RB_STENCIL_INFO 0x00008881
4118 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
4119 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
4120
4121 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
4122 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
4123 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)4124 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
4125 {
4126 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
4127 }
4128
4129 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
4130 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
4131 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)4132 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
4133 {
4134 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
4135 }
4136
4137 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
4138
4139 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
4140
4141 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
4142 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
4143 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)4144 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
4145 {
4146 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
4147 }
4148
4149 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
4150 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000
4151 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)4152 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
4153 {
4154 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
4155 }
4156
4157 #define REG_A6XX_RB_STENCILREF 0x00008887
4158 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
4159 #define A6XX_RB_STENCILREF_REF__SHIFT 0
A6XX_RB_STENCILREF_REF(uint32_t val)4160 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
4161 {
4162 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
4163 }
4164 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
4165 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8
A6XX_RB_STENCILREF_BFREF(uint32_t val)4166 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
4167 {
4168 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
4169 }
4170
4171 #define REG_A6XX_RB_STENCILMASK 0x00008888
4172 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
4173 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0
A6XX_RB_STENCILMASK_MASK(uint32_t val)4174 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
4175 {
4176 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
4177 }
4178 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
4179 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
A6XX_RB_STENCILMASK_BFMASK(uint32_t val)4180 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
4181 {
4182 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
4183 }
4184
4185 #define REG_A6XX_RB_STENCILWRMASK 0x00008889
4186 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
4187 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)4188 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
4189 {
4190 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
4191 }
4192 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
4193 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)4194 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
4195 {
4196 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
4197 }
4198
4199 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
4200 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff
4201 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET_X(uint32_t val)4202 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
4203 {
4204 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
4205 }
4206 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000
4207 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)4208 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
4209 {
4210 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
4211 }
4212
4213 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
4214 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001
4215 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
4216
4217 #define REG_A6XX_RB_LRZ_CNTL 0x00008898
4218 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
4219
4220 #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
4221 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
4222 #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
A6XX_RB_Z_CLAMP_MIN(float val)4223 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
4224 {
4225 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
4226 }
4227
4228 #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
4229 #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
4230 #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
A6XX_RB_Z_CLAMP_MAX(float val)4231 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
4232 {
4233 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
4234 }
4235
4236 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
4237 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff
4238 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0
A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)4239 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
4240 {
4241 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
4242 }
4243 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000
4244 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16
A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)4245 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
4246 {
4247 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
4248 }
4249
4250 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
4251 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff
4252 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)4253 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
4254 {
4255 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
4256 }
4257 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000
4258 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)4259 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
4260 {
4261 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
4262 }
4263
4264 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
4265 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff
4266 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)4267 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
4268 {
4269 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
4270 }
4271 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000
4272 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)4273 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
4274 {
4275 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
4276 }
4277
4278 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
4279 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f
4280 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)4281 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
4282 {
4283 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
4284 }
4285 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
4286 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)4287 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
4288 {
4289 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
4290 }
4291
4292 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
4293 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff
4294 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)4295 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
4296 {
4297 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
4298 }
4299 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000
4300 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)4301 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
4302 {
4303 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
4304 }
4305
4306 #define REG_A6XX_RB_MSAA_CNTL 0x000088d5
4307 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
4308 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)4309 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4310 {
4311 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
4312 }
4313
4314 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
4315 #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000
4316 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12
A6XX_RB_BLIT_BASE_GMEM(uint32_t val)4317 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
4318 {
4319 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
4320 }
4321
4322 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
4323 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
4324 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)4325 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4326 {
4327 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
4328 }
4329 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
4330 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
4331 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)4332 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4333 {
4334 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
4335 }
4336 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
4337 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)4338 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4339 {
4340 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
4341 }
4342 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
4343 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)4344 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4345 {
4346 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
4347 }
4348 #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
4349
4350 #define REG_A6XX_RB_BLIT_DST 0x000088d8
4351 #define A6XX_RB_BLIT_DST__MASK 0xffffffff
4352 #define A6XX_RB_BLIT_DST__SHIFT 0
A6XX_RB_BLIT_DST(uint32_t val)4353 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
4354 {
4355 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
4356 }
4357
4358 #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
4359
4360 #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
4361
4362 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
4363 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
4364 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_PITCH(uint32_t val)4365 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
4366 {
4367 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
4368 }
4369
4370 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
4371 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff
4372 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)4373 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
4374 {
4375 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
4376 }
4377
4378 #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
4379 #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
4380 #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
A6XX_RB_BLIT_FLAG_DST(uint32_t val)4381 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
4382 {
4383 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
4384 }
4385
4386 #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
4387
4388 #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
4389
4390 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
4391 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
4392 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)4393 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
4394 {
4395 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
4396 }
4397 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
4398 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)4399 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
4400 {
4401 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
4402 }
4403
4404 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
4405
4406 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
4407
4408 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
4409
4410 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
4411
4412 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
4413 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
4414 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002
4415 #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
4416 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
4417 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
4418 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)4419 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
4420 {
4421 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
4422 }
4423 #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300
4424 #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8
A6XX_RB_BLIT_INFO_UNK8(uint32_t val)4425 static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
4426 {
4427 return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
4428 }
4429 #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000
4430 #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12
A6XX_RB_BLIT_INFO_UNK12(uint32_t val)4431 static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
4432 {
4433 return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
4434 }
4435
4436 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
4437
4438 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
4439 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff
4440 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)4441 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
4442 {
4443 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
4444 }
4445
4446 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
4447 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
4448 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4449 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4450 {
4451 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
4452 }
4453 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
4454 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4455 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4456 {
4457 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4458 }
4459
4460 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
4461
4462 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
4463
4464 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
4465
4466 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
4467 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
4468 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)4469 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
4470 {
4471 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
4472 }
4473
4474 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
4475 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
4476 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4477 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4478 {
4479 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
4480 }
4481 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
4482 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)4483 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
4484 {
4485 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
4486 }
4487 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800
4488 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4489 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4490 {
4491 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4492 }
4493
REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0)4494 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4495
REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0)4496 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4497
REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0)4498 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
4499
REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0)4500 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4501 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
4502 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)4503 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
4504 {
4505 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
4506 }
4507
REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0)4508 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
4509 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
4510 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4511 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4512 {
4513 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
4514 }
4515 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
4516 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4517 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4518 {
4519 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4520 }
4521
4522 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
4523
4524 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
4525
4526 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
4527 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
4528 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)4529 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
4530 {
4531 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
4532 }
4533
4534 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
4535 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
4536 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)4537 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
4538 {
4539 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
4540 }
4541 #define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK 0x00000078
4542 #define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT 3
A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)4543 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)
4544 {
4545 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK;
4546 }
4547 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
4548 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
4549 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)4550 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
4551 {
4552 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
4553 }
4554 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
4555 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000
4556 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)4557 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
4558 {
4559 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
4560 }
4561 #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
4562 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
4563 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)4564 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
4565 {
4566 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
4567 }
4568 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
4569 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)4570 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
4571 {
4572 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
4573 }
4574 #define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK 0x20000000
4575 #define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT 29
A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)4576 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)
4577 {
4578 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK;
4579 }
4580
4581 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
4582
4583 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
4584 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4585 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)4586 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4587 {
4588 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4589 }
4590 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
4591 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)4592 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4593 {
4594 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
4595 }
4596 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4597 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)4598 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4599 {
4600 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4601 }
4602 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
4603 #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
4604 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
4605 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)4606 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4607 {
4608 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4609 }
4610 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
4611 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
4612 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
4613 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
4614
4615 #define REG_A6XX_RB_2D_DST_LO 0x00008c18
4616
4617 #define REG_A6XX_RB_2D_DST_HI 0x00008c19
4618
4619 #define REG_A6XX_RB_2D_DST 0x00008c18
4620 #define A6XX_RB_2D_DST__MASK 0xffffffff
4621 #define A6XX_RB_2D_DST__SHIFT 0
A6XX_RB_2D_DST(uint32_t val)4622 static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
4623 {
4624 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4625 }
4626
4627 #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
4628 #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
4629 #define A6XX_RB_2D_DST_PITCH__SHIFT 0
A6XX_RB_2D_DST_PITCH(uint32_t val)4630 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
4631 {
4632 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
4633 }
4634
4635 #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
4636 #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff
4637 #define A6XX_RB_2D_DST_PLANE1__SHIFT 0
A6XX_RB_2D_DST_PLANE1(uint32_t val)4638 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
4639 {
4640 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
4641 }
4642
4643 #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
4644 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
4645 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)4646 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
4647 {
4648 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
4649 }
4650
4651 #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
4652 #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
4653 #define A6XX_RB_2D_DST_PLANE2__SHIFT 0
A6XX_RB_2D_DST_PLANE2(uint32_t val)4654 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4655 {
4656 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4657 }
4658
4659 #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
4660
4661 #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
4662
4663 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
4664 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
4665 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0
A6XX_RB_2D_DST_FLAGS(uint32_t val)4666 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4667 {
4668 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4669 }
4670
4671 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
4672 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
4673 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)4674 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
4675 {
4676 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
4677 }
4678
4679 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
4680 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff
4681 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)4682 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
4683 {
4684 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
4685 }
4686
4687 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
4688 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
4689 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)4690 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
4691 {
4692 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
4693 }
4694
4695 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
4696
4697 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
4698
4699 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
4700
4701 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
4702
4703 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
4704
4705 #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
4706
4707 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
4708
4709 #define REG_A6XX_RB_CCU_CNTL 0x00008e07
4710 #define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000
4711 #define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23
A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)4712 static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
4713 {
4714 return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
4715 }
4716 #define A6XX_RB_CCU_CNTL_GMEM 0x00400000
4717 #define A6XX_RB_CCU_CNTL_UNK2 0x00000004
4718
4719 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
4720 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
4721 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
4722 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)4723 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4724 {
4725 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4726 }
4727 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
4728 #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010
4729 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400
4730 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10
A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)4731 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4732 {
4733 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4734 }
4735 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4736 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4737 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)4738 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4739 {
4740 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4741 }
4742
4743 #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
4744
4745 #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
4746
4747 #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
4748
4749 #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
4750
4751 #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
4752
4753 #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
4754
4755 #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
4756
4757 #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
4758
4759 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
4760
4761 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
4762
4763 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
4764
4765 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
4766
4767 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
4768
4769 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4770
4771 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
4772
4773 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
4774
4775 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
4776
4777 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
4778
4779 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4780
4781 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4782
4783 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4784
4785 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4786 #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff
4787 #define A6XX_RB_UNKNOWN_8E51__SHIFT 0
A6XX_RB_UNKNOWN_8E51(uint32_t val)4788 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4789 {
4790 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4791 }
4792
4793 #define REG_A6XX_VPC_UNKNOWN_9100 0x00009100
4794
4795 #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
4796 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4797 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)4798 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4799 {
4800 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4801 }
4802 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4803 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4804 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4805 {
4806 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4807 }
4808 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4809 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4810 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4811 {
4812 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4813 }
4814
4815 #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102
4816 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4817 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)4818 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4819 {
4820 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4821 }
4822 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4823 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4824 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4825 {
4826 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4827 }
4828 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4829 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4830 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4831 {
4832 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4833 }
4834
4835 #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103
4836 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4837 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)4838 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4839 {
4840 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4841 }
4842 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4843 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4844 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4845 {
4846 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4847 }
4848 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4849 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4850 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4851 {
4852 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4853 }
4854
4855 #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
4856 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4857 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)4858 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4859 {
4860 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4861 }
4862 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4863 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)4864 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4865 {
4866 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4867 }
4868
4869 #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
4870 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4871 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)4872 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4873 {
4874 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4875 }
4876 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4877 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)4878 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4879 {
4880 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4881 }
4882
4883 #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
4884 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4885 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)4886 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4887 {
4888 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4889 }
4890 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4891 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)4892 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4893 {
4894 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4895 }
4896
4897 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4898
4899 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4900 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4901 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)4902 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4903 {
4904 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4905 }
4906
REG_A6XX_VPC_VARYING_INTERP(uint32_t i0)4907 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4908
REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0)4909 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4910
REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0)4911 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4912
REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0)4913 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4914
4915 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
4916
4917 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4918
REG_A6XX_VPC_VAR(uint32_t i0)4919 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4920
REG_A6XX_VPC_VAR_DISABLE(uint32_t i0)4921 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4922
4923 #define REG_A6XX_VPC_SO_CNTL 0x00009216
4924 #define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff
4925 #define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0
A6XX_VPC_SO_CNTL_UNK0(uint32_t val)4926 static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
4927 {
4928 return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
4929 }
4930 #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
4931
4932 #define REG_A6XX_VPC_SO_PROG 0x00009217
4933 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4934 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
A6XX_VPC_SO_PROG_A_BUF(uint32_t val)4935 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4936 {
4937 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4938 }
4939 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
4940 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
A6XX_VPC_SO_PROG_A_OFF(uint32_t val)4941 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4942 {
4943 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4944 }
4945 #define A6XX_VPC_SO_PROG_A_EN 0x00000800
4946 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
4947 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
A6XX_VPC_SO_PROG_B_BUF(uint32_t val)4948 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4949 {
4950 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4951 }
4952 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4953 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
A6XX_VPC_SO_PROG_B_OFF(uint32_t val)4954 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4955 {
4956 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4957 }
4958 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
4959
4960 #define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
4961
4962 #define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
4963
4964 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4965 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4966 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)4967 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4968 {
4969 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4970 }
4971
REG_A6XX_VPC_SO(uint32_t i0)4972 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4973
REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0)4974 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4975 #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4976 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
A6XX_VPC_SO_BUFFER_BASE(uint32_t val)4977 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4978 {
4979 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4980 }
4981
REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0)4982 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4983
REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0)4984 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4985
REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0)4986 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4987 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4988 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)4989 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4990 {
4991 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4992 }
4993
REG_A6XX_VPC_SO_NCOMP(uint32_t i0)4994 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4995
REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0)4996 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4997 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc
4998 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2
A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)4999 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
5000 {
5001 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
5002 }
5003
REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0)5004 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5005 #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
5006 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
A6XX_VPC_SO_FLUSH_BASE(uint32_t val)5007 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
5008 {
5009 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
5010 }
5011
REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0)5012 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5013
REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0)5014 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
5015
5016 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
5017 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
5018
5019 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
5020
5021 #define REG_A6XX_VPC_VS_PACK 0x00009301
5022 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5023 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)5024 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
5025 {
5026 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
5027 }
5028 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00
5029 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)5030 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
5031 {
5032 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
5033 }
5034 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
5035 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)5036 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
5037 {
5038 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
5039 }
5040 #define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000
5041 #define A6XX_VPC_VS_PACK_UNK24__SHIFT 24
A6XX_VPC_VS_PACK_UNK24(uint32_t val)5042 static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
5043 {
5044 return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
5045 }
5046
5047 #define REG_A6XX_VPC_GS_PACK 0x00009302
5048 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5049 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)5050 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
5051 {
5052 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
5053 }
5054 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00
5055 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)5056 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
5057 {
5058 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
5059 }
5060 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
5061 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)5062 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
5063 {
5064 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
5065 }
5066 #define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000
5067 #define A6XX_VPC_GS_PACK_UNK24__SHIFT 24
A6XX_VPC_GS_PACK_UNK24(uint32_t val)5068 static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
5069 {
5070 return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
5071 }
5072
5073 #define REG_A6XX_VPC_DS_PACK 0x00009303
5074 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5075 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)5076 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
5077 {
5078 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
5079 }
5080 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00
5081 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)5082 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
5083 {
5084 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
5085 }
5086 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
5087 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)5088 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
5089 {
5090 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
5091 }
5092 #define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000
5093 #define A6XX_VPC_DS_PACK_UNK24__SHIFT 24
A6XX_VPC_DS_PACK_UNK24(uint32_t val)5094 static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
5095 {
5096 return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
5097 }
5098
5099 #define REG_A6XX_VPC_CNTL_0 0x00009304
5100 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
5101 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)5102 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
5103 {
5104 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
5105 }
5106 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
5107 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)5108 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
5109 {
5110 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
5111 }
5112 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
5113 #define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000
5114 #define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24
A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)5115 static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
5116 {
5117 return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
5118 }
5119
5120 #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
5121 #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
5122 #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
5123 #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
5124 #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
5125 #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
5126 #define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000
5127 #define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16
A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)5128 static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
5129 {
5130 return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
5131 }
5132
5133 #define REG_A6XX_VPC_SO_DISABLE 0x00009306
5134 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
5135
5136 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
5137
5138 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
5139
5140 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
5141
5142 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
5143
5144 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
5145
5146 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
5147
5148 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
5149
5150 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
5151
5152 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
5153
5154 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
5155
5156 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
5157
5158 #define REG_A6XX_PC_UNKNOWN_9801 0x00009801
5159 #define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff
5160 #define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0
A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)5161 static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
5162 {
5163 return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
5164 }
5165 #define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000
5166 #define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13
A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)5167 static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
5168 {
5169 return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
5170 }
5171
5172 #define REG_A6XX_PC_TESS_CNTL 0x00009802
5173 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
5174 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)5175 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
5176 {
5177 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
5178 }
5179 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
5180 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)5181 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
5182 {
5183 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
5184 }
5185
5186 #define REG_A6XX_PC_RESTART_INDEX 0x00009803
5187
5188 #define REG_A6XX_PC_MODE_CNTL 0x00009804
5189
5190 #define REG_A6XX_PC_UNKNOWN_9805 0x00009805
5191
5192 #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
5193
5194 #define REG_A6XX_PC_DRAW_CMD 0x00009840
5195 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
5196 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)5197 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
5198 {
5199 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
5200 }
5201
5202 #define REG_A6XX_PC_DISPATCH_CMD 0x00009841
5203 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
5204 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)5205 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
5206 {
5207 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
5208 }
5209
5210 #define REG_A6XX_PC_EVENT_CMD 0x00009842
5211 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
5212 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)5213 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
5214 {
5215 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
5216 }
5217 #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
5218 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)5219 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
5220 {
5221 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
5222 }
5223
5224 #define REG_A6XX_PC_POLYGON_MODE 0x00009981
5225 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
5226 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)5227 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
5228 {
5229 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
5230 }
5231
5232 #define REG_A6XX_PC_UNKNOWN_9980 0x00009980
5233
5234 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
5235 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
5236 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
5237 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
5238 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
5239
5240 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
5241 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5242 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5243 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5244 {
5245 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5246 }
5247 #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100
5248 #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200
5249 #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400
5250 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5251 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5252 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)5253 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
5254 {
5255 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
5256 }
5257
5258 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
5259 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5260 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5261 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5262 {
5263 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5264 }
5265 #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100
5266 #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200
5267 #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400
5268 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5269 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5270 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)5271 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
5272 {
5273 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
5274 }
5275
5276 #define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
5277
5278 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
5279 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5280 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5281 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5282 {
5283 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5284 }
5285 #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100
5286 #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200
5287 #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400
5288 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5289 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5290 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)5291 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
5292 {
5293 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
5294 }
5295
5296 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
5297 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
5298 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)5299 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
5300 {
5301 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
5302 }
5303 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
5304 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)5305 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
5306 {
5307 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
5308 }
5309 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
5310 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)5311 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
5312 {
5313 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
5314 }
5315 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000
5316 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18
A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)5317 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
5318 {
5319 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
5320 }
5321
5322 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
5323 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
5324 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)5325 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
5326 {
5327 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
5328 }
5329
5330 #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
5331
5332 #define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08
5333
5334 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
5335 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
5336 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)5337 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
5338 {
5339 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
5340 }
5341 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
5342 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)5343 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
5344 {
5345 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
5346 }
5347
5348 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
5349
5350 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
5351
5352 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
5353
5354 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
5355
5356 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
5357 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
5358 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
A6XX_PC_TESSFACTOR_ADDR(uint32_t val)5359 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
5360 {
5361 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
5362 }
5363
5364 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
5365 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
5366 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)5367 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
5368 {
5369 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
5370 }
5371 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
5372 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)5373 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
5374 {
5375 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
5376 }
5377 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
5378 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)5379 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
5380 {
5381 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
5382 }
5383
5384 #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
5385 #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff
5386 #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0
A6XX_PC_BIN_PRIM_STRM(uint32_t val)5387 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
5388 {
5389 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
5390 }
5391
5392 #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
5393 #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
5394 #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
A6XX_PC_BIN_DRAW_STRM(uint32_t val)5395 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
5396 {
5397 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
5398 }
5399
5400 #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
5401
5402 #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
5403
5404 #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
5405
5406 #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
5407
5408 #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
5409
5410 #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
5411
5412 #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
5413
5414 #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
5415
5416 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
5417
5418 #define REG_A6XX_VFD_CONTROL_0 0x0000a000
5419 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
5420 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)5421 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
5422 {
5423 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
5424 }
5425 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
5426 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)5427 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
5428 {
5429 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
5430 }
5431
5432 #define REG_A6XX_VFD_CONTROL_1 0x0000a001
5433 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
5434 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)5435 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
5436 {
5437 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
5438 }
5439 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
5440 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)5441 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
5442 {
5443 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
5444 }
5445 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
5446 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)5447 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
5448 {
5449 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
5450 }
5451
5452 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
5453 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
5454 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)5455 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
5456 {
5457 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
5458 }
5459 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
5460 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)5461 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
5462 {
5463 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
5464 }
5465
5466 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
5467 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
5468 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)5469 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
5470 {
5471 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
5472 }
5473 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
5474 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)5475 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
5476 {
5477 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
5478 }
5479 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
5480 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)5481 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
5482 {
5483 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
5484 }
5485
5486 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
5487
5488 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
5489 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
5490 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)5491 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5492 {
5493 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5494 }
5495
5496 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
5497 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
5498
5499 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
5500 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
5501
5502 #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
5503
5504 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
5505 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
5506 #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
5507
5508 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
5509
5510 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
5511
REG_A6XX_VFD_FETCH(uint32_t i0)5512 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5513
REG_A6XX_VFD_FETCH_BASE(uint32_t i0)5514 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5515
REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0)5516 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5517
REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0)5518 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
5519
REG_A6XX_VFD_FETCH_SIZE(uint32_t i0)5520 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5521
REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0)5522 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
5523
REG_A6XX_VFD_DECODE(uint32_t i0)5524 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5525
REG_A6XX_VFD_DECODE_INSTR(uint32_t i0)5526 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5527 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
5528 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)5529 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
5530 {
5531 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
5532 }
5533 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
5534 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)5535 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
5536 {
5537 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
5538 }
5539 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
5540 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
5541 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)5542 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
5543 {
5544 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
5545 }
5546 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
5547 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)5548 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
5549 {
5550 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
5551 }
5552 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
5553 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
5554
REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0)5555 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
5556
REG_A6XX_VFD_DEST_CNTL(uint32_t i0)5557 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5558
REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0)5559 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5560 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
5561 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)5562 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
5563 {
5564 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
5565 }
5566 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
5567 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)5568 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
5569 {
5570 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
5571 }
5572
5573 #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
5574
5575 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
5576 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5577 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5578 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5579 {
5580 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5581 }
5582 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5583 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5584 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5585 {
5586 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5587 }
5588 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5589 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)5590 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5591 {
5592 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5593 }
5594 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5595 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)5596 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5597 {
5598 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
5599 }
5600 #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
5601 #define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
5602 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
5603 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
5604
5605 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
5606
5607 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
5608 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5609 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)5610 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5611 {
5612 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5613 }
5614
REG_A6XX_SP_VS_OUT(uint32_t i0)5615 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5616
REG_A6XX_SP_VS_OUT_REG(uint32_t i0)5617 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5618 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
5619 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)5620 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
5621 {
5622 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
5623 }
5624 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5625 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)5626 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
5627 {
5628 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
5629 }
5630 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
5631 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)5632 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
5633 {
5634 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
5635 }
5636 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5637 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)5638 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
5639 {
5640 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
5641 }
5642
REG_A6XX_SP_VS_VPC_DST(uint32_t i0)5643 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5644
REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0)5645 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5646 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5647 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)5648 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
5649 {
5650 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
5651 }
5652 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5653 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)5654 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
5655 {
5656 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
5657 }
5658 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5659 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)5660 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
5661 {
5662 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
5663 }
5664 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5665 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)5666 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5667 {
5668 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5669 }
5670
5671 #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
5672
5673 #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
5674
5675 #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
5676
5677 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5678
5679 #define REG_A6XX_SP_VS_CONFIG 0x0000a823
5680 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5681 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5682 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5683 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5684 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
5685 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
5686 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
A6XX_SP_VS_CONFIG_NTEX(uint32_t val)5687 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
5688 {
5689 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5690 }
5691 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5692 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)5693 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5694 {
5695 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5696 }
5697 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
5698 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
A6XX_SP_VS_CONFIG_NIBO(uint32_t val)5699 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5700 {
5701 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5702 }
5703
5704 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5705
5706 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5707 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5708 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5709 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5710 {
5711 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5712 }
5713 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5714 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5715 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5716 {
5717 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5718 }
5719 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5720 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)5721 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5722 {
5723 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5724 }
5725 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5726 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)5727 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5728 {
5729 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
5730 }
5731 #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
5732 #define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
5733 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
5734 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
5735
5736 #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
5737
5738 #define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
5739
5740 #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
5741
5742 #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
5743
5744 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5745
5746 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5747 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5748 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5749 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5750 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5751 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
5752 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
5753 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
A6XX_SP_HS_CONFIG_NTEX(uint32_t val)5754 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
5755 {
5756 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5757 }
5758 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5759 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)5760 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5761 {
5762 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5763 }
5764 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
5765 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
A6XX_SP_HS_CONFIG_NIBO(uint32_t val)5766 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5767 {
5768 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5769 }
5770
5771 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5772
5773 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5774 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5775 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5776 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5777 {
5778 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5779 }
5780 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5781 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5782 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5783 {
5784 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5785 }
5786 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5787 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)5788 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5789 {
5790 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5791 }
5792 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5793 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)5794 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5795 {
5796 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
5797 }
5798 #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
5799 #define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
5800 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
5801 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
5802
5803 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5804 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5805 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)5806 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5807 {
5808 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5809 }
5810
REG_A6XX_SP_DS_OUT(uint32_t i0)5811 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5812
REG_A6XX_SP_DS_OUT_REG(uint32_t i0)5813 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5814 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5815 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)5816 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5817 {
5818 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5819 }
5820 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5821 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)5822 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5823 {
5824 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5825 }
5826 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
5827 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)5828 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5829 {
5830 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5831 }
5832 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5833 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)5834 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5835 {
5836 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5837 }
5838
REG_A6XX_SP_DS_VPC_DST(uint32_t i0)5839 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5840
REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0)5841 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5842 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5843 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)5844 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5845 {
5846 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5847 }
5848 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5849 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)5850 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5851 {
5852 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5853 }
5854 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5855 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)5856 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5857 {
5858 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5859 }
5860 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5861 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)5862 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5863 {
5864 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5865 }
5866
5867 #define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
5868
5869 #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
5870
5871 #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
5872
5873 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5874
5875 #define REG_A6XX_SP_DS_CONFIG 0x0000a863
5876 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5877 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5878 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5879 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5880 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
5881 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
5882 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
A6XX_SP_DS_CONFIG_NTEX(uint32_t val)5883 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
5884 {
5885 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5886 }
5887 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5888 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)5889 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5890 {
5891 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5892 }
5893 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
5894 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
A6XX_SP_DS_CONFIG_NIBO(uint32_t val)5895 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5896 {
5897 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5898 }
5899
5900 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5901
5902 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5903 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5904 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5905 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5906 {
5907 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5908 }
5909 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5910 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5911 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5912 {
5913 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5914 }
5915 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5916 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)5917 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5918 {
5919 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5920 }
5921 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5922 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)5923 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5924 {
5925 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
5926 }
5927 #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
5928 #define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
5929 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
5930 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
5931
5932 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5933
5934 #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5935
5936 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5937 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5938 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)5939 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5940 {
5941 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5942 }
5943 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5944 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5945 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5946 {
5947 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5948 }
5949
REG_A6XX_SP_GS_OUT(uint32_t i0)5950 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5951
REG_A6XX_SP_GS_OUT_REG(uint32_t i0)5952 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5953 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
5954 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)5955 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5956 {
5957 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5958 }
5959 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5960 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)5961 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5962 {
5963 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5964 }
5965 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
5966 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)5967 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5968 {
5969 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5970 }
5971 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5972 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)5973 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5974 {
5975 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5976 }
5977
REG_A6XX_SP_GS_VPC_DST(uint32_t i0)5978 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5979
REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0)5980 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5981 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5982 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)5983 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5984 {
5985 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5986 }
5987 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5988 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)5989 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5990 {
5991 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5992 }
5993 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5994 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)5995 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5996 {
5997 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5998 }
5999 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
6000 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)6001 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
6002 {
6003 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
6004 }
6005
6006 #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
6007
6008 #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
6009
6010 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
6011
6012 #define REG_A6XX_SP_GS_CONFIG 0x0000a894
6013 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
6014 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
6015 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
6016 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
6017 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
6018 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
6019 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
A6XX_SP_GS_CONFIG_NTEX(uint32_t val)6020 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
6021 {
6022 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
6023 }
6024 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
6025 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)6026 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
6027 {
6028 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
6029 }
6030 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
6031 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
A6XX_SP_GS_CONFIG_NIBO(uint32_t val)6032 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
6033 {
6034 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
6035 }
6036
6037 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
6038
6039 #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
6040
6041 #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
6042
6043 #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
6044
6045 #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
6046
6047 #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
6048
6049 #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
6050
6051 #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
6052
6053 #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
6054
6055 #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
6056
6057 #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
6058
6059 #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
6060
6061 #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
6062
6063 #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
6064
6065 #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
6066
6067 #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
6068
6069 #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
6070
6071 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
6072 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6073 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)6074 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6075 {
6076 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6077 }
6078 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6079 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)6080 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6081 {
6082 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6083 }
6084 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6085 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)6086 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6087 {
6088 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
6089 }
6090 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6091 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)6092 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6093 {
6094 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6095 }
6096 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6097 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6098 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6099 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
6100
6101 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
6102
6103 #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
6104
6105 #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
6106
6107 #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
6108
6109 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
6110 #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
6111 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
6112 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
6113 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
6114
6115 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
6116 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
6117 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
6118 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
6119 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
6120 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
6121 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
6122 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
6123 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
6124
6125 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
6126 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
6127 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)6128 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
6129 {
6130 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
6131 }
6132 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
6133 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)6134 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
6135 {
6136 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
6137 }
6138 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
6139 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)6140 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
6141 {
6142 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
6143 }
6144 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
6145 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)6146 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
6147 {
6148 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
6149 }
6150 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
6151 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)6152 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
6153 {
6154 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
6155 }
6156 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
6157 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)6158 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
6159 {
6160 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
6161 }
6162 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
6163 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)6164 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
6165 {
6166 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
6167 }
6168 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
6169 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)6170 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
6171 {
6172 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
6173 }
6174
6175 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
6176 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
6177 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
6178 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)6179 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
6180 {
6181 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
6182 }
6183 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
6184 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)6185 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
6186 {
6187 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
6188 }
6189 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000
6190 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)6191 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
6192 {
6193 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
6194 }
6195
6196 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
6197 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
6198 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)6199 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
6200 {
6201 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6202 }
6203
REG_A6XX_SP_FS_MRT(uint32_t i0)6204 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6205
REG_A6XX_SP_FS_MRT_REG(uint32_t i0)6206 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6207 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
6208 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)6209 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
6210 {
6211 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
6212 }
6213 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
6214 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
6215
6216 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
6217 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
6218 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)6219 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6220 {
6221 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6222 }
6223 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
6224 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
6225 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)6226 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
6227 {
6228 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6229 }
6230
REG_A6XX_SP_FS_PREFETCH(uint32_t i0)6231 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6232
REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0)6233 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6234 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
6235 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)6236 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6237 {
6238 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
6239 }
6240 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
6241 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)6242 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6243 {
6244 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
6245 }
6246 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
6247 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)6248 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
6249 {
6250 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
6251 }
6252 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
6253 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)6254 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
6255 {
6256 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
6257 }
6258 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
6259 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)6260 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
6261 {
6262 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
6263 }
6264 #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
6265 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000
6266 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27
A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)6267 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
6268 {
6269 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6270 }
6271
REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0)6272 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6273
REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0)6274 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6275 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff
6276 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)6277 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6278 {
6279 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6280 }
6281 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000
6282 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)6283 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6284 {
6285 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6286 }
6287
6288 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
6289
6290 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
6291
6292 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6293 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001
6294 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0
A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)6295 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
6296 {
6297 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
6298 }
6299
6300 #define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
6301
6302 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6303
6304 #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
6305
6306 #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
6307
6308 #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
6309
6310 #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
6311
6312 #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
6313
6314 #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
6315
6316 #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
6317
6318 #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
6319
REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0)6320 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6321
REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0)6322 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6323
REG_A6XX_SP_FS_OUTPUT(uint32_t i0)6324 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6325
REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0)6326 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6327 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6328 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)6329 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6330 {
6331 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
6332 }
6333 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6334
6335 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6336 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6337 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)6338 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6339 {
6340 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6341 }
6342 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6343 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)6344 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6345 {
6346 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6347 }
6348 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6349 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)6350 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6351 {
6352 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6353 }
6354 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6355 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)6356 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6357 {
6358 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6359 }
6360 #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
6361 #define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
6362 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
6363 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6364
6365 #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
6366
6367 #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
6368
6369 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6370 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6371 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6372 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6373 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6374 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6375 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6376 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
A6XX_SP_CS_CONFIG_NTEX(uint32_t val)6377 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6378 {
6379 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6380 }
6381 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6382 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)6383 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6384 {
6385 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6386 }
6387 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
6388 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
A6XX_SP_CS_CONFIG_NIBO(uint32_t val)6389 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6390 {
6391 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6392 }
6393
6394 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6395
6396 #define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
6397
6398 #define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
6399
6400 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6401
6402 #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
6403
6404 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6405 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6406 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6407 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6408 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6409 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6410 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6411 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
A6XX_SP_FS_CONFIG_NTEX(uint32_t val)6412 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6413 {
6414 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6415 }
6416 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6417 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)6418 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6419 {
6420 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6421 }
6422 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
6423 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
A6XX_SP_FS_CONFIG_NIBO(uint32_t val)6424 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6425 {
6426 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6427 }
6428
6429 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6430
REG_A6XX_SP_BINDLESS_BASE(uint32_t i0)6431 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6432
REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0)6433 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6434
6435 #define REG_A6XX_SP_IBO_LO 0x0000ab1a
6436
6437 #define REG_A6XX_SP_IBO_HI 0x0000ab1b
6438
6439 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6440
6441 #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6442 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6443 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6444 #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6445 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6446 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)6447 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6448 {
6449 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6450 }
6451 #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800
6452 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
6453 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)6454 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6455 {
6456 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6457 }
6458
6459 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6460
6461 #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6462
6463 #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
6464
6465 #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
6466
6467 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6468
6469 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6470
6471 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6472
6473 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6474 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6475 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6476 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6477 {
6478 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6479 }
6480
6481 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6482 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6483 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6484 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6485 {
6486 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6487 }
6488 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6489
6490 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6491
6492 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
6493
6494 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
6495
6496 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6497 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6498 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6499
6500 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6501 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6502 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)6503 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6504 {
6505 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6506 }
6507 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
6508 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)6509 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6510 {
6511 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6512 }
6513 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
6514 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)6515 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6516 {
6517 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6518 }
6519 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
6520 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)6521 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6522 {
6523 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6524 }
6525 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
6526 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)6527 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6528 {
6529 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6530 }
6531 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
6532 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)6533 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6534 {
6535 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6536 }
6537 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
6538 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)6539 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6540 {
6541 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6542 }
6543 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
6544 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)6545 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6546 {
6547 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6548 }
6549
6550 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
6551 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
6552 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)6553 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6554 {
6555 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6556 }
6557 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
6558 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)6559 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6560 {
6561 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6562 }
6563 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
6564 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)6565 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6566 {
6567 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6568 }
6569 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
6570 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)6571 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6572 {
6573 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6574 }
6575 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
6576 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)6577 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6578 {
6579 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6580 }
6581 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
6582 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)6583 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6584 {
6585 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6586 }
6587 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
6588 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)6589 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6590 {
6591 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6592 }
6593 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6594 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)6595 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6596 {
6597 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6598 }
6599
6600 #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6601
6602 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6603 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6604 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)6605 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6606 {
6607 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
6608 }
6609 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
6610 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)6611 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
6612 {
6613 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
6614 }
6615 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
6616 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)6617 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
6618 {
6619 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
6620 }
6621 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
6622 #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6623 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6624 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)6625 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6626 {
6627 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6628 }
6629 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6630 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6631 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6632 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6633
6634 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6635 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
6636 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)6637 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6638 {
6639 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6640 }
6641 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
6642 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)6643 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6644 {
6645 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6646 }
6647
6648 #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
6649
6650 #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
6651
6652 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6653
6654 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6655 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
6656 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)6657 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6658 {
6659 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6660 }
6661
6662 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
6663
6664 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
6665
6666 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6667
6668 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6669 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
6670 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)6671 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
6672 {
6673 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
6674 }
6675 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
6676 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)6677 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
6678 {
6679 return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
6680 }
6681
6682 #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
6683
6684 #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
6685
6686 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6687 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
6688 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)6689 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6690 {
6691 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6692 }
6693 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
6694
6695 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
6696 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
6697 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)6698 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
6699 {
6700 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
6701 }
6702 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
6703
6704 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
6705 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
6706 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)6707 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
6708 {
6709 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
6710 }
6711 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
6712
6713 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
6714 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
6715 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)6716 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
6717 {
6718 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6719 }
6720 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
6721
6722 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6723
6724 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6725
6726 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6727
6728 #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
6729
6730 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6731
6732 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
6733 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
6734 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)6735 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6736 {
6737 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
6738 }
6739 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
6740 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)6741 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
6742 {
6743 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
6744 }
6745 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
6746 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)6747 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
6748 {
6749 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
6750 }
6751 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
6752 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)6753 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
6754 {
6755 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
6756 }
6757
6758 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
6759 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
6760 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)6761 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
6762 {
6763 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
6764 }
6765 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
6766 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)6767 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
6768 {
6769 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
6770 }
6771 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
6772 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)6773 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
6774 {
6775 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
6776 }
6777 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
6778 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)6779 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
6780 {
6781 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
6782 }
6783
6784 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
6785 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
6786 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)6787 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
6788 {
6789 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
6790 }
6791 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
6792 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)6793 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
6794 {
6795 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
6796 }
6797 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
6798 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)6799 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
6800 {
6801 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
6802 }
6803 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
6804 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)6805 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6806 {
6807 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6808 }
6809
6810 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6811
6812 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6813 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
6814 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)6815 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6816 {
6817 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6818 }
6819 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
6820
6821 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
6822 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
6823 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)6824 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
6825 {
6826 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
6827 }
6828 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
6829 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)6830 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
6831 {
6832 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
6833 }
6834 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
6835 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)6836 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
6837 {
6838 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
6839 }
6840 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
6841 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)6842 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
6843 {
6844 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
6845 }
6846
6847 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
6848 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
6849 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)6850 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
6851 {
6852 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
6853 }
6854
6855 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
6856 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
6857 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)6858 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
6859 {
6860 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
6861 }
6862
6863 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
6864 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
6865 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)6866 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
6867 {
6868 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
6869 }
6870
6871 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
6872 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
6873 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)6874 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
6875 {
6876 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
6877 }
6878
6879 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
6880 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
6881 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)6882 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
6883 {
6884 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
6885 }
6886
6887 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
6888 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
6889 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)6890 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
6891 {
6892 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
6893 }
6894
6895 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
6896 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6897 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)6898 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6899 {
6900 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6901 }
6902 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
6903 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)6904 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
6905 {
6906 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
6907 }
6908 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
6909 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)6910 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
6911 {
6912 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
6913 }
6914 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6915 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)6916 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6917 {
6918 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6919 }
6920
6921 #define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
6922
6923 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6924
6925 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
6926
6927 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
6928
6929 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6930
6931 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6932
6933 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6934
REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0)6935 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6936
REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0)6937 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6938
6939 #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
6940 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
6941 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)6942 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
6943 {
6944 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
6945 }
6946
6947 #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
6948 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
6949 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)6950 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
6951 {
6952 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
6953 }
6954
6955 #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
6956 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
6957 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)6958 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
6959 {
6960 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
6961 }
6962 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
6963 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)6964 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
6965 {
6966 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
6967 }
6968
6969 #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08
6970 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
6971 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
6972 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
6973 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
6974 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
6975 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
6976 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
6977 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
6978 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000
6979 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100
6980 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00
6981 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)6982 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
6983 {
6984 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
6985 }
6986 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000
6987 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14
A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)6988 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
6989 {
6990 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
6991 }
6992
6993 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
6994 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
6995 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)6996 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
6997 {
6998 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
6999 }
7000 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
7001
7002 #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
7003 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
7004
REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0)7005 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7006
REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0)7007 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7008
7009 #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
7010 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
7011 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)7012 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
7013 {
7014 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
7015 }
7016 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
7017 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)7018 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
7019 {
7020 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
7021 }
7022
7023 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
7024
7025 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
7026
7027 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
7028
7029 #define REG_A6XX_CP_EVENT_START 0x0000d600
7030 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
7031 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_EVENT_START_STATE_ID(uint32_t val)7032 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7033 {
7034 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7035 }
7036
7037 #define REG_A6XX_CP_EVENT_END 0x0000d601
7038 #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
7039 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_EVENT_END_STATE_ID(uint32_t val)7040 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
7041 {
7042 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
7043 }
7044
7045 #define REG_A6XX_CP_2D_EVENT_START 0x0000d700
7046 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
7047 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)7048 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
7049 {
7050 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
7051 }
7052
7053 #define REG_A6XX_CP_2D_EVENT_END 0x0000d701
7054 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
7055 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)7056 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
7057 {
7058 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
7059 }
7060
7061 #define REG_A6XX_TEX_SAMP_0 0x00000000
7062 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
7063 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
7064 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)7065 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
7066 {
7067 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
7068 }
7069 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
7070 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)7071 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
7072 {
7073 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
7074 }
7075 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
7076 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)7077 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
7078 {
7079 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
7080 }
7081 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
7082 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)7083 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
7084 {
7085 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
7086 }
7087 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
7088 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)7089 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
7090 {
7091 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
7092 }
7093 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
7094 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)7095 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
7096 {
7097 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
7098 }
7099 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
7100 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
A6XX_TEX_SAMP_0_LOD_BIAS(float val)7101 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
7102 {
7103 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
7104 }
7105
7106 #define REG_A6XX_TEX_SAMP_1 0x00000001
7107 #define A6XX_TEX_SAMP_1_UNK0 0x00000001
7108 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
7109 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)7110 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
7111 {
7112 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
7113 }
7114 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
7115 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
7116 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
7117 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
7118 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
A6XX_TEX_SAMP_1_MAX_LOD(float val)7119 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
7120 {
7121 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
7122 }
7123 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
7124 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
A6XX_TEX_SAMP_1_MIN_LOD(float val)7125 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
7126 {
7127 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
7128 }
7129
7130 #define REG_A6XX_TEX_SAMP_2 0x00000002
7131 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7132 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)7133 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7134 {
7135 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7136 }
7137 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7138 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
7139 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)7140 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
7141 {
7142 return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
7143 }
7144
7145 #define REG_A6XX_TEX_SAMP_3 0x00000003
7146
7147 #define REG_A6XX_TEX_CONST_0 0x00000000
7148 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7149 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)7150 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
7151 {
7152 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
7153 }
7154 #define A6XX_TEX_CONST_0_SRGB 0x00000004
7155 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
7156 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)7157 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
7158 {
7159 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
7160 }
7161 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
7162 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)7163 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
7164 {
7165 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
7166 }
7167 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
7168 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)7169 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
7170 {
7171 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
7172 }
7173 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
7174 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)7175 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
7176 {
7177 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
7178 }
7179 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
7180 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)7181 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
7182 {
7183 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
7184 }
7185 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
7186 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
7187 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
7188 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)7189 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7190 {
7191 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7192 }
7193 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
7194 #define A6XX_TEX_CONST_0_FMT__SHIFT 22
A6XX_TEX_CONST_0_FMT(enum a6xx_format val)7195 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
7196 {
7197 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
7198 }
7199 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
7200 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30
A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)7201 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
7202 {
7203 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
7204 }
7205
7206 #define REG_A6XX_TEX_CONST_1 0x00000001
7207 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
7208 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
A6XX_TEX_CONST_1_WIDTH(uint32_t val)7209 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
7210 {
7211 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
7212 }
7213 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
7214 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
A6XX_TEX_CONST_1_HEIGHT(uint32_t val)7215 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
7216 {
7217 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
7218 }
7219
7220 #define REG_A6XX_TEX_CONST_2 0x00000002
7221 #define A6XX_TEX_CONST_2_UNK4 0x00000010
7222 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
7223 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)7224 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
7225 {
7226 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
7227 }
7228 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
7229 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
A6XX_TEX_CONST_2_PITCH(uint32_t val)7230 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
7231 {
7232 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
7233 }
7234 #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
7235 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29
A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)7236 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
7237 {
7238 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
7239 }
7240 #define A6XX_TEX_CONST_2_UNK31 0x80000000
7241
7242 #define REG_A6XX_TEX_CONST_3 0x00000003
7243 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
7244 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)7245 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
7246 {
7247 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
7248 }
7249 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
7250 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)7251 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7252 {
7253 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7254 }
7255 #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
7256 #define A6XX_TEX_CONST_3_FLAG 0x10000000
7257
7258 #define REG_A6XX_TEX_CONST_4 0x00000004
7259 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
7260 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
A6XX_TEX_CONST_4_BASE_LO(uint32_t val)7261 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
7262 {
7263 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
7264 }
7265
7266 #define REG_A6XX_TEX_CONST_5 0x00000005
7267 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
7268 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
A6XX_TEX_CONST_5_BASE_HI(uint32_t val)7269 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
7270 {
7271 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
7272 }
7273 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
7274 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
A6XX_TEX_CONST_5_DEPTH(uint32_t val)7275 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
7276 {
7277 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
7278 }
7279
7280 #define REG_A6XX_TEX_CONST_6 0x00000006
7281 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
7282 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)7283 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7284 {
7285 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7286 }
7287
7288 #define REG_A6XX_TEX_CONST_7 0x00000007
7289 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
7290 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)7291 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
7292 {
7293 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
7294 }
7295
7296 #define REG_A6XX_TEX_CONST_8 0x00000008
7297 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
7298 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)7299 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
7300 {
7301 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
7302 }
7303
7304 #define REG_A6XX_TEX_CONST_9 0x00000009
7305 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7306 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)7307 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7308 {
7309 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7310 }
7311
7312 #define REG_A6XX_TEX_CONST_10 0x0000000a
7313 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7314 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)7315 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7316 {
7317 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7318 }
7319 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
7320 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)7321 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7322 {
7323 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7324 }
7325 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
7326 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)7327 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7328 {
7329 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7330 }
7331
7332 #define REG_A6XX_TEX_CONST_11 0x0000000b
7333
7334 #define REG_A6XX_TEX_CONST_12 0x0000000c
7335
7336 #define REG_A6XX_TEX_CONST_13 0x0000000d
7337
7338 #define REG_A6XX_TEX_CONST_14 0x0000000e
7339
7340 #define REG_A6XX_TEX_CONST_15 0x0000000f
7341
7342 #define REG_A6XX_IBO_0 0x00000000
7343 #define A6XX_IBO_0_TILE_MODE__MASK 0x00000003
7344 #define A6XX_IBO_0_TILE_MODE__SHIFT 0
A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)7345 static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
7346 {
7347 return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
7348 }
7349 #define A6XX_IBO_0_FMT__MASK 0x3fc00000
7350 #define A6XX_IBO_0_FMT__SHIFT 22
A6XX_IBO_0_FMT(enum a6xx_format val)7351 static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
7352 {
7353 return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
7354 }
7355
7356 #define REG_A6XX_IBO_1 0x00000001
7357 #define A6XX_IBO_1_WIDTH__MASK 0x00007fff
7358 #define A6XX_IBO_1_WIDTH__SHIFT 0
A6XX_IBO_1_WIDTH(uint32_t val)7359 static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
7360 {
7361 return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
7362 }
7363 #define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000
7364 #define A6XX_IBO_1_HEIGHT__SHIFT 15
A6XX_IBO_1_HEIGHT(uint32_t val)7365 static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
7366 {
7367 return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
7368 }
7369
7370 #define REG_A6XX_IBO_2 0x00000002
7371 #define A6XX_IBO_2_UNK4 0x00000010
7372 #define A6XX_IBO_2_PITCH__MASK 0x1fffff80
7373 #define A6XX_IBO_2_PITCH__SHIFT 7
A6XX_IBO_2_PITCH(uint32_t val)7374 static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
7375 {
7376 return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
7377 }
7378 #define A6XX_IBO_2_TYPE__MASK 0x60000000
7379 #define A6XX_IBO_2_TYPE__SHIFT 29
A6XX_IBO_2_TYPE(enum a6xx_tex_type val)7380 static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
7381 {
7382 return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
7383 }
7384 #define A6XX_IBO_2_UNK31 0x80000000
7385
7386 #define REG_A6XX_IBO_3 0x00000003
7387 #define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff
7388 #define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0
A6XX_IBO_3_ARRAY_PITCH(uint32_t val)7389 static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
7390 {
7391 return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
7392 }
7393 #define A6XX_IBO_3_UNK27 0x08000000
7394 #define A6XX_IBO_3_FLAG 0x10000000
7395
7396 #define REG_A6XX_IBO_4 0x00000004
7397 #define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
7398 #define A6XX_IBO_4_BASE_LO__SHIFT 0
A6XX_IBO_4_BASE_LO(uint32_t val)7399 static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
7400 {
7401 return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
7402 }
7403
7404 #define REG_A6XX_IBO_5 0x00000005
7405 #define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff
7406 #define A6XX_IBO_5_BASE_HI__SHIFT 0
A6XX_IBO_5_BASE_HI(uint32_t val)7407 static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
7408 {
7409 return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
7410 }
7411 #define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000
7412 #define A6XX_IBO_5_DEPTH__SHIFT 17
A6XX_IBO_5_DEPTH(uint32_t val)7413 static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
7414 {
7415 return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
7416 }
7417
7418 #define REG_A6XX_IBO_6 0x00000006
7419
7420 #define REG_A6XX_IBO_7 0x00000007
7421
7422 #define REG_A6XX_IBO_8 0x00000008
7423
7424 #define REG_A6XX_IBO_9 0x00000009
7425 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7426 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)7427 static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7428 {
7429 return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7430 }
7431
7432 #define REG_A6XX_IBO_10 0x0000000a
7433 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7434 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)7435 static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
7436 {
7437 return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
7438 }
7439
7440 #define REG_A6XX_UBO_0 0x00000000
7441 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
7442 #define A6XX_UBO_0_BASE_LO__SHIFT 0
A6XX_UBO_0_BASE_LO(uint32_t val)7443 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
7444 {
7445 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
7446 }
7447
7448 #define REG_A6XX_UBO_1 0x00000001
7449 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
7450 #define A6XX_UBO_1_BASE_HI__SHIFT 0
A6XX_UBO_1_BASE_HI(uint32_t val)7451 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
7452 {
7453 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
7454 }
7455 #define A6XX_UBO_1_SIZE__MASK 0xfffe0000
7456 #define A6XX_UBO_1_SIZE__SHIFT 17
A6XX_UBO_1_SIZE(uint32_t val)7457 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
7458 {
7459 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
7460 }
7461
7462 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
7463
7464 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
7465
7466 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
7467
7468 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
7469
7470 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
7471
7472 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
7473
7474 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
7475
7476 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
7477
7478 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
7479
7480 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
7481
7482 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
7483
7484 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
7485
7486 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
7487
7488 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
7489
7490 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
7491
7492 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
7493
7494 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
7495
7496 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
7497
7498 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
7499
7500 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
7501
7502 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
7503
7504 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
7505
7506 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
7507
7508 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
7509
7510 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
7511
7512 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
7513
7514 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
7515
7516 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
7517 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
7518 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)7519 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
7520 {
7521 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
7522 }
7523 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
7524 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)7525 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
7526 {
7527 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
7528 }
7529
7530 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
7531
7532 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
7533
7534 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
7535
7536 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
7537 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
7538 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)7539 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
7540 {
7541 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
7542 }
7543 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
7544 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)7545 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
7546 {
7547 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
7548 }
7549 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
7550 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)7551 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
7552 {
7553 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
7554 }
7555
7556 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
7557 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
7558 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)7559 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
7560 {
7561 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
7562 }
7563
7564 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
7565
7566 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
7567
7568 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
7569
7570 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
7571
7572 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
7573
7574 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
7575
7576 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
7577
7578 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
7579
7580 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
7581 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
7582 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)7583 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
7584 {
7585 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
7586 }
7587 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
7588 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)7589 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
7590 {
7591 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
7592 }
7593 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
7594 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)7595 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
7596 {
7597 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
7598 }
7599 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
7600 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)7601 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
7602 {
7603 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
7604 }
7605 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
7606 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)7607 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
7608 {
7609 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
7610 }
7611 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
7612 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)7613 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
7614 {
7615 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
7616 }
7617 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
7618 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)7619 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
7620 {
7621 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
7622 }
7623 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
7624 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)7625 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
7626 {
7627 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
7628 }
7629
7630 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
7631 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
7632 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)7633 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
7634 {
7635 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
7636 }
7637 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
7638 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)7639 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
7640 {
7641 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
7642 }
7643 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
7644 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)7645 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
7646 {
7647 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
7648 }
7649 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
7650 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)7651 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
7652 {
7653 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
7654 }
7655 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
7656 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)7657 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
7658 {
7659 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
7660 }
7661 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
7662 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)7663 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
7664 {
7665 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
7666 }
7667 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
7668 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)7669 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
7670 {
7671 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
7672 }
7673 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
7674 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)7675 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
7676 {
7677 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
7678 }
7679
7680 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
7681
7682 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
7683
7684 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
7685
7686 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
7687
7688
7689 #endif /* A6XX_XML */
7690