1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef __DPU_IO_UTIL_H__ 6 #define __DPU_IO_UTIL_H__ 7 8 #include <linux/platform_device.h> 9 #include <linux/types.h> 10 11 #define DEV_DBG(fmt, args...) pr_debug(fmt, ##args) 12 #define DEV_INFO(fmt, args...) pr_info(fmt, ##args) 13 #define DEV_WARN(fmt, args...) pr_warn(fmt, ##args) 14 #define DEV_ERR(fmt, args...) pr_err(fmt, ##args) 15 16 enum dss_clk_type { 17 DSS_CLK_AHB, /* no set rate. rate controlled through rpm */ 18 DSS_CLK_PCLK, 19 }; 20 21 struct dss_clk { 22 struct clk *clk; /* clk handle */ 23 char clk_name[32]; 24 enum dss_clk_type type; 25 unsigned long rate; 26 unsigned long max_rate; 27 }; 28 29 struct dss_module_power { 30 unsigned int num_clk; 31 struct dss_clk *clk_config; 32 }; 33 34 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk); 35 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); 36 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk); 37 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); 38 int msm_dss_parse_clock(struct platform_device *pdev, 39 struct dss_module_power *mp); 40 #endif /* __DPU_IO_UTIL_H__ */ 41