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Searched refs:DISPC_CONFIG (Results 1 – 4 of 4) sorted by relevance

/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; in mgr_fld_write()
1045 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); in dispc_enable_gamma_table()
1243 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
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Ddispc.h19 #define DISPC_CONFIG 0x0044 macro
/drivers/gpu/drm/omapdrm/dss/
Ddispc.c265 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
266 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
267 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
268 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
288 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
289 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
291 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
1499 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
2931 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2965 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
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Ddispc.h17 #define DISPC_CONFIG 0x0044 macro