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Searched refs:DISPC_CONTROL (Results 1 – 4 of 4) sorted by relevance

/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; in mgr_fld_write()
2810 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2818 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
[all …]
Ddispc.h18 #define DISPC_CONTROL 0x0040 macro
/drivers/gpu/drm/omapdrm/dss/
Ddispc.c260 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
261 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
262 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
263 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
264 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
283 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
285 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
2895 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2903 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2911 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
[all …]
Ddispc.h16 #define DISPC_CONTROL 0x0040 macro