1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24
25 Copyright (C) 2013-2020 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum vgt_event_type {
52 VS_DEALLOC = 0,
53 PS_DEALLOC = 1,
54 VS_DONE_TS = 2,
55 PS_DONE_TS = 3,
56 CACHE_FLUSH_TS = 4,
57 CONTEXT_DONE = 5,
58 CACHE_FLUSH = 6,
59 VIZQUERY_START = 7,
60 HLSQ_FLUSH = 7,
61 VIZQUERY_END = 8,
62 SC_WAIT_WC = 9,
63 WRITE_PRIMITIVE_COUNTS = 9,
64 START_PRIMITIVE_CTRS = 11,
65 STOP_PRIMITIVE_CTRS = 12,
66 RST_PIX_CNT = 13,
67 RST_VTX_CNT = 14,
68 TILE_FLUSH = 15,
69 STAT_EVENT = 16,
70 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
71 ZPASS_DONE = 21,
72 CACHE_FLUSH_AND_INV_EVENT = 22,
73 RB_DONE_TS = 22,
74 PERFCOUNTER_START = 23,
75 PERFCOUNTER_STOP = 24,
76 VS_FETCH_DONE = 27,
77 FACENESS_FLUSH = 28,
78 WT_DONE_TS = 8,
79 FLUSH_SO_0 = 17,
80 FLUSH_SO_1 = 18,
81 FLUSH_SO_2 = 19,
82 FLUSH_SO_3 = 20,
83 PC_CCU_INVALIDATE_DEPTH = 24,
84 PC_CCU_INVALIDATE_COLOR = 25,
85 PC_CCU_RESOLVE_TS = 26,
86 PC_CCU_FLUSH_DEPTH_TS = 28,
87 PC_CCU_FLUSH_COLOR_TS = 29,
88 BLIT = 30,
89 UNK_25 = 37,
90 LRZ_FLUSH = 38,
91 BLIT_OP_FILL_2D = 39,
92 BLIT_OP_COPY_2D = 40,
93 BLIT_OP_SCALE_2D = 42,
94 CONTEXT_DONE_2D = 43,
95 UNK_2C = 44,
96 UNK_2D = 45,
97 CACHE_INVALIDATE = 49,
98 };
99
100 enum pc_di_primtype {
101 DI_PT_NONE = 0,
102 DI_PT_POINTLIST_PSIZE = 1,
103 DI_PT_LINELIST = 2,
104 DI_PT_LINESTRIP = 3,
105 DI_PT_TRILIST = 4,
106 DI_PT_TRIFAN = 5,
107 DI_PT_TRISTRIP = 6,
108 DI_PT_LINELOOP = 7,
109 DI_PT_RECTLIST = 8,
110 DI_PT_POINTLIST = 9,
111 DI_PT_LINE_ADJ = 10,
112 DI_PT_LINESTRIP_ADJ = 11,
113 DI_PT_TRI_ADJ = 12,
114 DI_PT_TRISTRIP_ADJ = 13,
115 DI_PT_PATCHES0 = 31,
116 DI_PT_PATCHES1 = 32,
117 DI_PT_PATCHES2 = 33,
118 DI_PT_PATCHES3 = 34,
119 DI_PT_PATCHES4 = 35,
120 DI_PT_PATCHES5 = 36,
121 DI_PT_PATCHES6 = 37,
122 DI_PT_PATCHES7 = 38,
123 DI_PT_PATCHES8 = 39,
124 DI_PT_PATCHES9 = 40,
125 DI_PT_PATCHES10 = 41,
126 DI_PT_PATCHES11 = 42,
127 DI_PT_PATCHES12 = 43,
128 DI_PT_PATCHES13 = 44,
129 DI_PT_PATCHES14 = 45,
130 DI_PT_PATCHES15 = 46,
131 DI_PT_PATCHES16 = 47,
132 DI_PT_PATCHES17 = 48,
133 DI_PT_PATCHES18 = 49,
134 DI_PT_PATCHES19 = 50,
135 DI_PT_PATCHES20 = 51,
136 DI_PT_PATCHES21 = 52,
137 DI_PT_PATCHES22 = 53,
138 DI_PT_PATCHES23 = 54,
139 DI_PT_PATCHES24 = 55,
140 DI_PT_PATCHES25 = 56,
141 DI_PT_PATCHES26 = 57,
142 DI_PT_PATCHES27 = 58,
143 DI_PT_PATCHES28 = 59,
144 DI_PT_PATCHES29 = 60,
145 DI_PT_PATCHES30 = 61,
146 DI_PT_PATCHES31 = 62,
147 };
148
149 enum pc_di_src_sel {
150 DI_SRC_SEL_DMA = 0,
151 DI_SRC_SEL_IMMEDIATE = 1,
152 DI_SRC_SEL_AUTO_INDEX = 2,
153 DI_SRC_SEL_AUTO_XFB = 3,
154 };
155
156 enum pc_di_face_cull_sel {
157 DI_FACE_CULL_NONE = 0,
158 DI_FACE_CULL_FETCH = 1,
159 DI_FACE_BACKFACE_CULL = 2,
160 DI_FACE_FRONTFACE_CULL = 3,
161 };
162
163 enum pc_di_index_size {
164 INDEX_SIZE_IGN = 0,
165 INDEX_SIZE_16_BIT = 0,
166 INDEX_SIZE_32_BIT = 1,
167 INDEX_SIZE_8_BIT = 2,
168 INDEX_SIZE_INVALID = 0,
169 };
170
171 enum pc_di_vis_cull_mode {
172 IGNORE_VISIBILITY = 0,
173 USE_VISIBILITY = 1,
174 };
175
176 enum adreno_pm4_packet_type {
177 CP_TYPE0_PKT = 0,
178 CP_TYPE1_PKT = 0x40000000,
179 CP_TYPE2_PKT = 0x80000000,
180 CP_TYPE3_PKT = 0xc0000000,
181 CP_TYPE4_PKT = 0x40000000,
182 CP_TYPE7_PKT = 0x70000000,
183 };
184
185 enum adreno_pm4_type3_packets {
186 CP_ME_INIT = 72,
187 CP_NOP = 16,
188 CP_PREEMPT_ENABLE = 28,
189 CP_PREEMPT_TOKEN = 30,
190 CP_INDIRECT_BUFFER = 63,
191 CP_INDIRECT_BUFFER_CHAIN = 87,
192 CP_INDIRECT_BUFFER_PFD = 55,
193 CP_WAIT_FOR_IDLE = 38,
194 CP_WAIT_REG_MEM = 60,
195 CP_WAIT_REG_EQ = 82,
196 CP_WAIT_REG_GTE = 83,
197 CP_WAIT_UNTIL_READ = 92,
198 CP_WAIT_IB_PFD_COMPLETE = 93,
199 CP_REG_RMW = 33,
200 CP_SET_BIN_DATA = 47,
201 CP_SET_BIN_DATA5 = 47,
202 CP_REG_TO_MEM = 62,
203 CP_MEM_WRITE = 61,
204 CP_MEM_WRITE_CNTR = 79,
205 CP_COND_EXEC = 68,
206 CP_COND_WRITE = 69,
207 CP_COND_WRITE5 = 69,
208 CP_EVENT_WRITE = 70,
209 CP_EVENT_WRITE_SHD = 88,
210 CP_EVENT_WRITE_CFL = 89,
211 CP_EVENT_WRITE_ZPD = 91,
212 CP_RUN_OPENCL = 49,
213 CP_DRAW_INDX = 34,
214 CP_DRAW_INDX_2 = 54,
215 CP_DRAW_INDX_BIN = 52,
216 CP_DRAW_INDX_2_BIN = 53,
217 CP_VIZ_QUERY = 35,
218 CP_SET_STATE = 37,
219 CP_SET_CONSTANT = 45,
220 CP_IM_LOAD = 39,
221 CP_IM_LOAD_IMMEDIATE = 43,
222 CP_LOAD_CONSTANT_CONTEXT = 46,
223 CP_INVALIDATE_STATE = 59,
224 CP_SET_SHADER_BASES = 74,
225 CP_SET_BIN_MASK = 80,
226 CP_SET_BIN_SELECT = 81,
227 CP_CONTEXT_UPDATE = 94,
228 CP_INTERRUPT = 64,
229 CP_IM_STORE = 44,
230 CP_SET_DRAW_INIT_FLAGS = 75,
231 CP_SET_PROTECTED_MODE = 95,
232 CP_BOOTSTRAP_UCODE = 111,
233 CP_LOAD_STATE = 48,
234 CP_LOAD_STATE4 = 48,
235 CP_COND_INDIRECT_BUFFER_PFE = 58,
236 CP_COND_INDIRECT_BUFFER_PFD = 50,
237 CP_INDIRECT_BUFFER_PFE = 63,
238 CP_SET_BIN = 76,
239 CP_TEST_TWO_MEMS = 113,
240 CP_REG_WR_NO_CTXT = 120,
241 CP_RECORD_PFP_TIMESTAMP = 17,
242 CP_SET_SECURE_MODE = 102,
243 CP_WAIT_FOR_ME = 19,
244 CP_SET_DRAW_STATE = 67,
245 CP_DRAW_INDX_OFFSET = 56,
246 CP_DRAW_INDIRECT = 40,
247 CP_DRAW_INDX_INDIRECT = 41,
248 CP_DRAW_INDIRECT_MULTI = 42,
249 CP_DRAW_AUTO = 36,
250 CP_UNKNOWN_19 = 25,
251 CP_UNKNOWN_1A = 26,
252 CP_UNKNOWN_4E = 78,
253 CP_WIDE_REG_WRITE = 116,
254 CP_SCRATCH_TO_REG = 77,
255 CP_REG_TO_SCRATCH = 74,
256 CP_WAIT_MEM_WRITES = 18,
257 CP_COND_REG_EXEC = 71,
258 CP_MEM_TO_REG = 66,
259 CP_EXEC_CS_INDIRECT = 65,
260 CP_EXEC_CS = 51,
261 CP_PERFCOUNTER_ACTION = 80,
262 CP_SMMU_TABLE_UPDATE = 83,
263 CP_SET_MARKER = 101,
264 CP_SET_PSEUDO_REG = 86,
265 CP_CONTEXT_REG_BUNCH = 92,
266 CP_YIELD_ENABLE = 28,
267 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
268 CP_SKIP_IB2_ENABLE_LOCAL = 35,
269 CP_SET_SUBDRAW_SIZE = 53,
270 CP_SET_VISIBILITY_OVERRIDE = 100,
271 CP_PREEMPT_ENABLE_GLOBAL = 105,
272 CP_PREEMPT_ENABLE_LOCAL = 106,
273 CP_CONTEXT_SWITCH_YIELD = 107,
274 CP_SET_RENDER_MODE = 108,
275 CP_COMPUTE_CHECKPOINT = 110,
276 CP_MEM_TO_MEM = 115,
277 CP_BLIT = 44,
278 CP_REG_TEST = 57,
279 CP_SET_MODE = 99,
280 CP_LOAD_STATE6_GEOM = 50,
281 CP_LOAD_STATE6_FRAG = 52,
282 CP_LOAD_STATE6 = 54,
283 IN_IB_PREFETCH_END = 23,
284 IN_SUBBLK_PREFETCH = 31,
285 IN_INSTR_PREFETCH = 32,
286 IN_INSTR_MATCH = 71,
287 IN_CONST_PREFETCH = 73,
288 IN_INCR_UPDT_STATE = 85,
289 IN_INCR_UPDT_CONST = 86,
290 IN_INCR_UPDT_INSTR = 87,
291 PKT4 = 4,
292 CP_SCRATCH_WRITE = 76,
293 CP_REG_TO_MEM_OFFSET_MEM = 116,
294 CP_REG_TO_MEM_OFFSET_REG = 114,
295 CP_WAIT_MEM_GTE = 20,
296 CP_WAIT_TWO_REGS = 112,
297 CP_MEMCPY = 117,
298 CP_SET_BIN_DATA5_OFFSET = 46,
299 CP_SET_CTXSWITCH_IB = 85,
300 CP_REG_WRITE = 109,
301 CP_WHERE_AM_I = 98,
302 };
303
304 enum adreno_state_block {
305 SB_VERT_TEX = 0,
306 SB_VERT_MIPADDR = 1,
307 SB_FRAG_TEX = 2,
308 SB_FRAG_MIPADDR = 3,
309 SB_VERT_SHADER = 4,
310 SB_GEOM_SHADER = 5,
311 SB_FRAG_SHADER = 6,
312 SB_COMPUTE_SHADER = 7,
313 };
314
315 enum adreno_state_type {
316 ST_SHADER = 0,
317 ST_CONSTANTS = 1,
318 };
319
320 enum adreno_state_src {
321 SS_DIRECT = 0,
322 SS_INVALID_ALL_IC = 2,
323 SS_INVALID_PART_IC = 3,
324 SS_INDIRECT = 4,
325 SS_INDIRECT_TCM = 5,
326 SS_INDIRECT_STM = 6,
327 };
328
329 enum a4xx_state_block {
330 SB4_VS_TEX = 0,
331 SB4_HS_TEX = 1,
332 SB4_DS_TEX = 2,
333 SB4_GS_TEX = 3,
334 SB4_FS_TEX = 4,
335 SB4_CS_TEX = 5,
336 SB4_VS_SHADER = 8,
337 SB4_HS_SHADER = 9,
338 SB4_DS_SHADER = 10,
339 SB4_GS_SHADER = 11,
340 SB4_FS_SHADER = 12,
341 SB4_CS_SHADER = 13,
342 SB4_SSBO = 14,
343 SB4_CS_SSBO = 15,
344 };
345
346 enum a4xx_state_type {
347 ST4_SHADER = 0,
348 ST4_CONSTANTS = 1,
349 ST4_UBO = 2,
350 };
351
352 enum a4xx_state_src {
353 SS4_DIRECT = 0,
354 SS4_INDIRECT = 2,
355 };
356
357 enum a6xx_state_block {
358 SB6_VS_TEX = 0,
359 SB6_HS_TEX = 1,
360 SB6_DS_TEX = 2,
361 SB6_GS_TEX = 3,
362 SB6_FS_TEX = 4,
363 SB6_CS_TEX = 5,
364 SB6_VS_SHADER = 8,
365 SB6_HS_SHADER = 9,
366 SB6_DS_SHADER = 10,
367 SB6_GS_SHADER = 11,
368 SB6_FS_SHADER = 12,
369 SB6_CS_SHADER = 13,
370 SB6_IBO = 14,
371 SB6_CS_IBO = 15,
372 };
373
374 enum a6xx_state_type {
375 ST6_SHADER = 0,
376 ST6_CONSTANTS = 1,
377 ST6_UBO = 2,
378 ST6_IBO = 3,
379 };
380
381 enum a6xx_state_src {
382 SS6_DIRECT = 0,
383 SS6_BINDLESS = 1,
384 SS6_INDIRECT = 2,
385 SS6_UBO = 3,
386 };
387
388 enum a4xx_index_size {
389 INDEX4_SIZE_8_BIT = 0,
390 INDEX4_SIZE_16_BIT = 1,
391 INDEX4_SIZE_32_BIT = 2,
392 };
393
394 enum a6xx_patch_type {
395 TESS_QUADS = 0,
396 TESS_TRIANGLES = 1,
397 TESS_ISOLINES = 2,
398 };
399
400 enum a6xx_draw_indirect_opcode {
401 INDIRECT_OP_NORMAL = 2,
402 INDIRECT_OP_INDEXED = 4,
403 };
404
405 enum cp_cond_function {
406 WRITE_ALWAYS = 0,
407 WRITE_LT = 1,
408 WRITE_LE = 2,
409 WRITE_EQ = 3,
410 WRITE_NE = 4,
411 WRITE_GE = 5,
412 WRITE_GT = 6,
413 };
414
415 enum render_mode_cmd {
416 BYPASS = 1,
417 BINNING = 2,
418 GMEM = 3,
419 BLIT2D = 5,
420 BLIT2DSCALE = 7,
421 END2D = 8,
422 };
423
424 enum cp_blit_cmd {
425 BLIT_OP_FILL = 0,
426 BLIT_OP_COPY = 1,
427 BLIT_OP_SCALE = 3,
428 };
429
430 enum a6xx_render_mode {
431 RM6_BYPASS = 1,
432 RM6_BINNING = 2,
433 RM6_GMEM = 4,
434 RM6_ENDVIS = 5,
435 RM6_RESOLVE = 6,
436 RM6_YIELD = 7,
437 RM6_COMPUTE = 8,
438 RM6_BLIT2DSCALE = 12,
439 RM6_IB1LIST_START = 13,
440 RM6_IB1LIST_END = 14,
441 RM6_IFPC_ENABLE = 256,
442 RM6_IFPC_DISABLE = 257,
443 };
444
445 enum pseudo_reg {
446 SMMU_INFO = 0,
447 NON_SECURE_SAVE_ADDR = 1,
448 SECURE_SAVE_ADDR = 2,
449 NON_PRIV_SAVE_ADDR = 3,
450 COUNTER = 4,
451 };
452
453 enum compare_mode {
454 PRED_TEST = 1,
455 REG_COMPARE = 2,
456 RENDER_MODE = 3,
457 };
458
459 enum ctxswitch_ib {
460 RESTORE_IB = 0,
461 YIELD_RESTORE_IB = 1,
462 SAVE_IB = 2,
463 RB_SAVE_IB = 3,
464 };
465
466 enum reg_tracker {
467 TRACK_CNTL_REG = 1,
468 TRACK_RENDER_CNTL = 2,
469 UNK_EVENT_WRITE = 4,
470 };
471
472 #define REG_CP_LOAD_STATE_0 0x00000000
473 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
474 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)475 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
476 {
477 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
478 }
479 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
480 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
482 {
483 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
484 }
485 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
486 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
488 {
489 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
490 }
491 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
492 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)493 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
494 {
495 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
496 }
497
498 #define REG_CP_LOAD_STATE_1 0x00000001
499 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
500 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
502 {
503 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
504 }
505 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
506 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)507 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
508 {
509 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
510 }
511
512 #define REG_CP_LOAD_STATE4_0 0x00000000
513 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
514 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
CP_LOAD_STATE4_0_DST_OFF(uint32_t val)515 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
516 {
517 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
518 }
519 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
520 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)521 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
522 {
523 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
524 }
525 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
526 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)527 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
528 {
529 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
530 }
531 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
532 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)533 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
534 {
535 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
536 }
537
538 #define REG_CP_LOAD_STATE4_1 0x00000001
539 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
540 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)541 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
542 {
543 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
544 }
545 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
546 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)547 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
548 {
549 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
550 }
551
552 #define REG_CP_LOAD_STATE4_2 0x00000002
553 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
554 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)555 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
556 {
557 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
558 }
559
560 #define REG_CP_LOAD_STATE6_0 0x00000000
561 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
562 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
CP_LOAD_STATE6_0_DST_OFF(uint32_t val)563 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
564 {
565 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
566 }
567 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
568 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)569 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
570 {
571 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
572 }
573 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
574 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)575 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
576 {
577 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
578 }
579 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
580 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)581 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
582 {
583 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
584 }
585 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
586 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)587 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
588 {
589 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
590 }
591
592 #define REG_CP_LOAD_STATE6_1 0x00000001
593 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
594 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)595 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
596 {
597 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
598 }
599
600 #define REG_CP_LOAD_STATE6_2 0x00000002
601 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
602 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)603 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
604 {
605 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
606 }
607
608 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
609
610 #define REG_CP_DRAW_INDX_0 0x00000000
611 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
612 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)613 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
614 {
615 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
616 }
617
618 #define REG_CP_DRAW_INDX_1 0x00000001
619 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
620 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)621 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
622 {
623 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
624 }
625 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
626 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)627 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
628 {
629 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
630 }
631 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
632 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)633 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
634 {
635 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
636 }
637 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
638 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)639 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
640 {
641 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
642 }
643 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
644 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
645 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
646 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
647 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)648 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
649 {
650 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
651 }
652
653 #define REG_CP_DRAW_INDX_2 0x00000002
654 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
655 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)656 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
657 {
658 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
659 }
660
661 #define REG_CP_DRAW_INDX_3 0x00000003
662 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
663 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
CP_DRAW_INDX_3_INDX_BASE(uint32_t val)664 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
665 {
666 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
667 }
668
669 #define REG_CP_DRAW_INDX_4 0x00000004
670 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
671 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)672 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
673 {
674 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
675 }
676
677 #define REG_CP_DRAW_INDX_2_0 0x00000000
678 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
679 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)680 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
681 {
682 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
683 }
684
685 #define REG_CP_DRAW_INDX_2_1 0x00000001
686 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
687 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)688 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
689 {
690 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
691 }
692 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
693 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)694 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
695 {
696 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
697 }
698 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
699 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)700 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
701 {
702 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
703 }
704 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
705 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)706 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
707 {
708 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
709 }
710 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
711 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
712 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
713 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
714 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)715 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
716 {
717 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
718 }
719
720 #define REG_CP_DRAW_INDX_2_2 0x00000002
721 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
722 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)723 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
724 {
725 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
726 }
727
728 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
729 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
730 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)731 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
732 {
733 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
734 }
735 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
736 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)737 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
738 {
739 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
740 }
741 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
742 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)743 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
744 {
745 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
746 }
747 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
748 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)749 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
750 {
751 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
752 }
753 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
754 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12
CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)755 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
756 {
757 return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
758 }
759 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
760 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
761
762 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
763 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
764 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)765 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
766 {
767 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
768 }
769
770 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
771 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
772 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)773 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
774 {
775 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
776 }
777
778 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
779 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
780 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)781 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
782 {
783 return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
784 }
785
786
787 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
788 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
789 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)790 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
791 {
792 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
793 }
794
795 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
796 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
797 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)798 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
799 {
800 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
801 }
802
803 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
804
805 #define REG_CP_DRAW_INDX_OFFSET_6 0x00000006
806 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
807 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)808 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
809 {
810 return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
811 }
812
813 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
814 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
815 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)816 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
817 {
818 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
819 }
820
821 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
822 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
823 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)824 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
825 {
826 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
827 }
828
829 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
830 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
831 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)832 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
833 {
834 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
835 }
836 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
837 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)838 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
839 {
840 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
841 }
842 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
843 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)844 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
845 {
846 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
847 }
848 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
849 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)850 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
851 {
852 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
853 }
854 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
855 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12
A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)856 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
857 {
858 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
859 }
860 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
861 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
862
863
864 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
865 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
866 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)867 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
868 {
869 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
870 }
871
872
873 #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
874 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
875 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)876 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
877 {
878 return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
879 }
880
881 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
882 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
883 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)884 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
885 {
886 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
887 }
888
889 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
890
891 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
892 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
893 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)894 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
895 {
896 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
897 }
898 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
899 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)900 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
901 {
902 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
903 }
904 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
905 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)906 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
907 {
908 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
909 }
910 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
911 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)912 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
913 {
914 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
915 }
916 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
917 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12
A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)918 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
919 {
920 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
921 }
922 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
923 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
924
925
926 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
927 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
928 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)929 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
930 {
931 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
932 }
933
934 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
935 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
936 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)937 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
938 {
939 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
940 }
941
942 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
943 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
944 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)945 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
946 {
947 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
948 }
949
950
951 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
952 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
953 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)954 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
955 {
956 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
957 }
958
959 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
960 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
961 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)962 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
963 {
964 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
965 }
966
967 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
968
969 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
970 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
971 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)972 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
973 {
974 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
975 }
976
977 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
978 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
979 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)980 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
981 {
982 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
983 }
984
985 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
986 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
987 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)988 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
989 {
990 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
991 }
992
993 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
994
995 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
996 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
997 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)998 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
999 {
1000 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1001 }
1002 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
1003 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6
A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)1004 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1005 {
1006 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1007 }
1008 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
1009 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8
A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)1010 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1011 {
1012 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1013 }
1014 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
1015 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10
A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)1016 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1017 {
1018 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1019 }
1020 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
1021 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12
A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)1022 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1023 {
1024 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1025 }
1026 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
1027 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
1028
1029 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
1030 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
1031 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)1032 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1033 {
1034 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1035 }
1036 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
1037 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8
A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)1038 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1039 {
1040 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1041 }
1042
1043 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002
1044 #define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
1045 #define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)1046 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
1047 {
1048 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
1049 }
1050
1051 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
1052
1053 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005
1054 #define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff
1055 #define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0
A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)1056 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
1057 {
1058 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
1059 }
1060
1061 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
1062
1063 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008
1064 #define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff
1065 #define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0
A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)1066 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
1067 {
1068 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
1069 }
1070
REG_CP_SET_DRAW_STATE_(uint32_t i0)1071 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1072
REG_CP_SET_DRAW_STATE__0(uint32_t i0)1073 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1074 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
1075 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
CP_SET_DRAW_STATE__0_COUNT(uint32_t val)1076 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
1077 {
1078 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
1079 }
1080 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
1081 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
1082 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
1083 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
1084 #define CP_SET_DRAW_STATE__0_BINNING 0x00100000
1085 #define CP_SET_DRAW_STATE__0_GMEM 0x00200000
1086 #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
1087 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
1088 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)1089 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
1090 {
1091 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
1092 }
1093
REG_CP_SET_DRAW_STATE__1(uint32_t i0)1094 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1095 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
1096 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)1097 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
1098 {
1099 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
1100 }
1101
REG_CP_SET_DRAW_STATE__2(uint32_t i0)1102 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1103 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
1104 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)1105 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
1106 {
1107 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
1108 }
1109
1110 #define REG_CP_SET_BIN_0 0x00000000
1111
1112 #define REG_CP_SET_BIN_1 0x00000001
1113 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
1114 #define CP_SET_BIN_1_X1__SHIFT 0
CP_SET_BIN_1_X1(uint32_t val)1115 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
1116 {
1117 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
1118 }
1119 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
1120 #define CP_SET_BIN_1_Y1__SHIFT 16
CP_SET_BIN_1_Y1(uint32_t val)1121 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
1122 {
1123 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
1124 }
1125
1126 #define REG_CP_SET_BIN_2 0x00000002
1127 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
1128 #define CP_SET_BIN_2_X2__SHIFT 0
CP_SET_BIN_2_X2(uint32_t val)1129 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
1130 {
1131 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
1132 }
1133 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
1134 #define CP_SET_BIN_2_Y2__SHIFT 16
CP_SET_BIN_2_Y2(uint32_t val)1135 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
1136 {
1137 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
1138 }
1139
1140 #define REG_CP_SET_BIN_DATA_0 0x00000000
1141 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
1142 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)1143 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
1144 {
1145 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
1146 }
1147
1148 #define REG_CP_SET_BIN_DATA_1 0x00000001
1149 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
1150 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)1151 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
1152 {
1153 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
1154 }
1155
1156 #define REG_CP_SET_BIN_DATA5_0 0x00000000
1157 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
1158 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)1159 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
1160 {
1161 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
1162 }
1163 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
1164 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)1165 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
1166 {
1167 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
1168 }
1169
1170 #define REG_CP_SET_BIN_DATA5_1 0x00000001
1171 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
1172 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)1173 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
1174 {
1175 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
1176 }
1177
1178 #define REG_CP_SET_BIN_DATA5_2 0x00000002
1179 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
1180 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)1181 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
1182 {
1183 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
1184 }
1185
1186 #define REG_CP_SET_BIN_DATA5_3 0x00000003
1187 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
1188 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)1189 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
1190 {
1191 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
1192 }
1193
1194 #define REG_CP_SET_BIN_DATA5_4 0x00000004
1195 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
1196 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)1197 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
1198 {
1199 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
1200 }
1201
1202 #define REG_CP_SET_BIN_DATA5_5 0x00000005
1203 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
1204 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)1205 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
1206 {
1207 return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
1208 }
1209
1210 #define REG_CP_SET_BIN_DATA5_6 0x00000006
1211 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
1212 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)1213 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
1214 {
1215 return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1216 }
1217
1218 #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
1219 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
1220 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16
CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)1221 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1222 {
1223 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1224 }
1225 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
1226 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22
CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)1227 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1228 {
1229 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1230 }
1231
1232 #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
1233 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
1234 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)1235 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1236 {
1237 return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1238 }
1239
1240 #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
1241 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
1242 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)1243 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1244 {
1245 return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1246 }
1247
1248 #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
1249 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
1250 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)1251 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1252 {
1253 return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1254 }
1255
1256 #define REG_CP_REG_RMW_0 0x00000000
1257 #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
1258 #define CP_REG_RMW_0_DST_REG__SHIFT 0
CP_REG_RMW_0_DST_REG(uint32_t val)1259 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1260 {
1261 return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1262 }
1263 #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
1264 #define CP_REG_RMW_0_ROTATE__SHIFT 24
CP_REG_RMW_0_ROTATE(uint32_t val)1265 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1266 {
1267 return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1268 }
1269 #define CP_REG_RMW_0_SRC1_ADD 0x20000000
1270 #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
1271 #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
1272
1273 #define REG_CP_REG_RMW_1 0x00000001
1274 #define CP_REG_RMW_1_SRC0__MASK 0xffffffff
1275 #define CP_REG_RMW_1_SRC0__SHIFT 0
CP_REG_RMW_1_SRC0(uint32_t val)1276 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1277 {
1278 return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1279 }
1280
1281 #define REG_CP_REG_RMW_2 0x00000002
1282 #define CP_REG_RMW_2_SRC1__MASK 0xffffffff
1283 #define CP_REG_RMW_2_SRC1__SHIFT 0
CP_REG_RMW_2_SRC1(uint32_t val)1284 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1285 {
1286 return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
1287 }
1288
1289 #define REG_CP_REG_TO_MEM_0 0x00000000
1290 #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
1291 #define CP_REG_TO_MEM_0_REG__SHIFT 0
CP_REG_TO_MEM_0_REG(uint32_t val)1292 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1293 {
1294 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1295 }
1296 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
1297 #define CP_REG_TO_MEM_0_CNT__SHIFT 18
CP_REG_TO_MEM_0_CNT(uint32_t val)1298 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1299 {
1300 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1301 }
1302 #define CP_REG_TO_MEM_0_64B 0x40000000
1303 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1304
1305 #define REG_CP_REG_TO_MEM_1 0x00000001
1306 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1307 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
CP_REG_TO_MEM_1_DEST(uint32_t val)1308 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1309 {
1310 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1311 }
1312
1313 #define REG_CP_REG_TO_MEM_2 0x00000002
1314 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1315 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
CP_REG_TO_MEM_2_DEST_HI(uint32_t val)1316 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1317 {
1318 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1319 }
1320
1321 #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
1322 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
1323 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)1324 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1325 {
1326 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1327 }
1328 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
1329 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18
CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)1330 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1331 {
1332 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1333 }
1334 #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
1335 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
1336
1337 #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
1338 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
1339 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)1340 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1341 {
1342 return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1343 }
1344
1345 #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
1346 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
1347 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)1348 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1349 {
1350 return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1351 }
1352
1353 #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
1354 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
1355 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)1356 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1357 {
1358 return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1359 }
1360 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
1361
1362 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
1363 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
1364 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)1365 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1366 {
1367 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1368 }
1369 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
1370 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18
CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)1371 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1372 {
1373 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1374 }
1375 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
1376 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
1377
1378 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
1379 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
1380 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)1381 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1382 {
1383 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1384 }
1385
1386 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
1387 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
1388 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)1389 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1390 {
1391 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1392 }
1393
1394 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
1395 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
1396 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)1397 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1398 {
1399 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1400 }
1401
1402 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
1403 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
1404 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)1405 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1406 {
1407 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1408 }
1409
1410 #define REG_CP_MEM_TO_REG_0 0x00000000
1411 #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
1412 #define CP_MEM_TO_REG_0_REG__SHIFT 0
CP_MEM_TO_REG_0_REG(uint32_t val)1413 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1414 {
1415 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1416 }
1417 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1418 #define CP_MEM_TO_REG_0_CNT__SHIFT 19
CP_MEM_TO_REG_0_CNT(uint32_t val)1419 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1420 {
1421 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1422 }
1423 #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
1424 #define CP_MEM_TO_REG_0_UNK31 0x80000000
1425
1426 #define REG_CP_MEM_TO_REG_1 0x00000001
1427 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1428 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
CP_MEM_TO_REG_1_SRC(uint32_t val)1429 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1430 {
1431 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1432 }
1433
1434 #define REG_CP_MEM_TO_REG_2 0x00000002
1435 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1436 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
CP_MEM_TO_REG_2_SRC_HI(uint32_t val)1437 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1438 {
1439 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1440 }
1441
1442 #define REG_CP_MEM_TO_MEM_0 0x00000000
1443 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1444 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1445 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1446 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1447 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
1448 #define CP_MEM_TO_MEM_0_UNK31 0x80000000
1449
1450 #define REG_CP_MEMCPY_0 0x00000000
1451 #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
1452 #define CP_MEMCPY_0_DWORDS__SHIFT 0
CP_MEMCPY_0_DWORDS(uint32_t val)1453 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1454 {
1455 return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1456 }
1457
1458 #define REG_CP_MEMCPY_1 0x00000001
1459 #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
1460 #define CP_MEMCPY_1_SRC_LO__SHIFT 0
CP_MEMCPY_1_SRC_LO(uint32_t val)1461 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1462 {
1463 return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1464 }
1465
1466 #define REG_CP_MEMCPY_2 0x00000002
1467 #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
1468 #define CP_MEMCPY_2_SRC_HI__SHIFT 0
CP_MEMCPY_2_SRC_HI(uint32_t val)1469 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1470 {
1471 return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1472 }
1473
1474 #define REG_CP_MEMCPY_3 0x00000003
1475 #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
1476 #define CP_MEMCPY_3_DST_LO__SHIFT 0
CP_MEMCPY_3_DST_LO(uint32_t val)1477 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1478 {
1479 return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1480 }
1481
1482 #define REG_CP_MEMCPY_4 0x00000004
1483 #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
1484 #define CP_MEMCPY_4_DST_HI__SHIFT 0
CP_MEMCPY_4_DST_HI(uint32_t val)1485 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1486 {
1487 return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1488 }
1489
1490 #define REG_CP_REG_TO_SCRATCH_0 0x00000000
1491 #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
1492 #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
CP_REG_TO_SCRATCH_0_REG(uint32_t val)1493 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1494 {
1495 return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1496 }
1497 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
1498 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20
CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)1499 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1500 {
1501 return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1502 }
1503 #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
1504 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24
CP_REG_TO_SCRATCH_0_CNT(uint32_t val)1505 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1506 {
1507 return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1508 }
1509
1510 #define REG_CP_SCRATCH_TO_REG_0 0x00000000
1511 #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
1512 #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
CP_SCRATCH_TO_REG_0_REG(uint32_t val)1513 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1514 {
1515 return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1516 }
1517 #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
1518 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
1519 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20
CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)1520 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1521 {
1522 return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1523 }
1524 #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
1525 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24
CP_SCRATCH_TO_REG_0_CNT(uint32_t val)1526 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1527 {
1528 return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1529 }
1530
1531 #define REG_CP_SCRATCH_WRITE_0 0x00000000
1532 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
1533 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20
CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)1534 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1535 {
1536 return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1537 }
1538
1539 #define REG_CP_MEM_WRITE_0 0x00000000
1540 #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
1541 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
CP_MEM_WRITE_0_ADDR_LO(uint32_t val)1542 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1543 {
1544 return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1545 }
1546
1547 #define REG_CP_MEM_WRITE_1 0x00000001
1548 #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
1549 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
CP_MEM_WRITE_1_ADDR_HI(uint32_t val)1550 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1551 {
1552 return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1553 }
1554
1555 #define REG_CP_COND_WRITE_0 0x00000000
1556 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1557 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)1558 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1559 {
1560 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1561 }
1562 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1563 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1564
1565 #define REG_CP_COND_WRITE_1 0x00000001
1566 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1567 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
CP_COND_WRITE_1_POLL_ADDR(uint32_t val)1568 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1569 {
1570 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1571 }
1572
1573 #define REG_CP_COND_WRITE_2 0x00000002
1574 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1575 #define CP_COND_WRITE_2_REF__SHIFT 0
CP_COND_WRITE_2_REF(uint32_t val)1576 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1577 {
1578 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1579 }
1580
1581 #define REG_CP_COND_WRITE_3 0x00000003
1582 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1583 #define CP_COND_WRITE_3_MASK__SHIFT 0
CP_COND_WRITE_3_MASK(uint32_t val)1584 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1585 {
1586 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1587 }
1588
1589 #define REG_CP_COND_WRITE_4 0x00000004
1590 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1591 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)1592 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1593 {
1594 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1595 }
1596
1597 #define REG_CP_COND_WRITE_5 0x00000005
1598 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1599 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
CP_COND_WRITE_5_WRITE_DATA(uint32_t val)1600 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1601 {
1602 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1603 }
1604
1605 #define REG_CP_COND_WRITE5_0 0x00000000
1606 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1607 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)1608 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1609 {
1610 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1611 }
1612 #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
1613 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1614 #define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020
1615 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1616
1617 #define REG_CP_COND_WRITE5_1 0x00000001
1618 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1619 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)1620 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1621 {
1622 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1623 }
1624
1625 #define REG_CP_COND_WRITE5_2 0x00000002
1626 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1627 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)1628 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1629 {
1630 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1631 }
1632
1633 #define REG_CP_COND_WRITE5_3 0x00000003
1634 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1635 #define CP_COND_WRITE5_3_REF__SHIFT 0
CP_COND_WRITE5_3_REF(uint32_t val)1636 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1637 {
1638 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1639 }
1640
1641 #define REG_CP_COND_WRITE5_4 0x00000004
1642 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1643 #define CP_COND_WRITE5_4_MASK__SHIFT 0
CP_COND_WRITE5_4_MASK(uint32_t val)1644 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1645 {
1646 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1647 }
1648
1649 #define REG_CP_COND_WRITE5_5 0x00000005
1650 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1651 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)1652 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1653 {
1654 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1655 }
1656
1657 #define REG_CP_COND_WRITE5_6 0x00000006
1658 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1659 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)1660 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1661 {
1662 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1663 }
1664
1665 #define REG_CP_COND_WRITE5_7 0x00000007
1666 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1667 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)1668 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1669 {
1670 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1671 }
1672
1673 #define REG_CP_WAIT_MEM_GTE_0 0x00000000
1674 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
1675 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)1676 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1677 {
1678 return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1679 }
1680
1681 #define REG_CP_WAIT_MEM_GTE_1 0x00000001
1682 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
1683 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)1684 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1685 {
1686 return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1687 }
1688
1689 #define REG_CP_WAIT_MEM_GTE_2 0x00000002
1690 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
1691 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)1692 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1693 {
1694 return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1695 }
1696
1697 #define REG_CP_WAIT_MEM_GTE_3 0x00000003
1698 #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
1699 #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
CP_WAIT_MEM_GTE_3_REF(uint32_t val)1700 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1701 {
1702 return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1703 }
1704
1705 #define REG_CP_WAIT_REG_MEM_0 0x00000000
1706 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
1707 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)1708 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1709 {
1710 return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1711 }
1712 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
1713 #define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010
1714 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020
1715 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
1716
1717 #define REG_CP_WAIT_REG_MEM_1 0x00000001
1718 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
1719 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)1720 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1721 {
1722 return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1723 }
1724
1725 #define REG_CP_WAIT_REG_MEM_2 0x00000002
1726 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
1727 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)1728 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1729 {
1730 return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1731 }
1732
1733 #define REG_CP_WAIT_REG_MEM_3 0x00000003
1734 #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
1735 #define CP_WAIT_REG_MEM_3_REF__SHIFT 0
CP_WAIT_REG_MEM_3_REF(uint32_t val)1736 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1737 {
1738 return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1739 }
1740
1741 #define REG_CP_WAIT_REG_MEM_4 0x00000004
1742 #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
1743 #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
CP_WAIT_REG_MEM_4_MASK(uint32_t val)1744 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1745 {
1746 return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1747 }
1748
1749 #define REG_CP_WAIT_REG_MEM_5 0x00000005
1750 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
1751 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)1752 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1753 {
1754 return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1755 }
1756
1757 #define REG_CP_WAIT_TWO_REGS_0 0x00000000
1758 #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
1759 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
CP_WAIT_TWO_REGS_0_REG0(uint32_t val)1760 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1761 {
1762 return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1763 }
1764
1765 #define REG_CP_WAIT_TWO_REGS_1 0x00000001
1766 #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
1767 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
CP_WAIT_TWO_REGS_1_REG1(uint32_t val)1768 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1769 {
1770 return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1771 }
1772
1773 #define REG_CP_WAIT_TWO_REGS_2 0x00000002
1774 #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
1775 #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
CP_WAIT_TWO_REGS_2_REF(uint32_t val)1776 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1777 {
1778 return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
1779 }
1780
1781 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1782
1783 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1784 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1785 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
CP_DISPATCH_COMPUTE_1_X(uint32_t val)1786 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1787 {
1788 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1789 }
1790
1791 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1792 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1793 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
CP_DISPATCH_COMPUTE_2_Y(uint32_t val)1794 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1795 {
1796 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1797 }
1798
1799 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1800 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1801 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
CP_DISPATCH_COMPUTE_3_Z(uint32_t val)1802 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1803 {
1804 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1805 }
1806
1807 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1808 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1809 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)1810 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1811 {
1812 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1813 }
1814
1815 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1816 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1817 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)1818 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1819 {
1820 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1821 }
1822
1823 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1824 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1825 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)1826 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1827 {
1828 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1829 }
1830
1831 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1832 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1833 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1834
1835 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1836
1837 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1838 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1839 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)1840 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1841 {
1842 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1843 }
1844
1845 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1846 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1847 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)1848 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1849 {
1850 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1851 }
1852
1853 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1854 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1855 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)1856 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1857 {
1858 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1859 }
1860
1861 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1862 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1863 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)1864 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1865 {
1866 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1867 }
1868
1869 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1870 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1871 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)1872 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1873 {
1874 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1875 }
1876
1877 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1878
1879 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1880 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1881 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)1882 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1883 {
1884 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1885 }
1886
1887 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1888
1889 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1890 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1891 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)1892 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1893 {
1894 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1895 }
1896
1897 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1898 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1899 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)1900 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1901 {
1902 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1903 }
1904
1905 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1906
1907 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1908
1909 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1910 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1911 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)1912 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1913 {
1914 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1915 }
1916
1917 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1918 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1919 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)1920 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1921 {
1922 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1923 }
1924
1925 #define REG_CP_EVENT_WRITE_0 0x00000000
1926 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1927 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)1928 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1929 {
1930 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1931 }
1932 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1933 #define CP_EVENT_WRITE_0_IRQ 0x80000000
1934
1935 #define REG_CP_EVENT_WRITE_1 0x00000001
1936 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1937 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)1938 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1939 {
1940 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1941 }
1942
1943 #define REG_CP_EVENT_WRITE_2 0x00000002
1944 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1945 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)1946 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1947 {
1948 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1949 }
1950
1951 #define REG_CP_EVENT_WRITE_3 0x00000003
1952
1953 #define REG_CP_BLIT_0 0x00000000
1954 #define CP_BLIT_0_OP__MASK 0x0000000f
1955 #define CP_BLIT_0_OP__SHIFT 0
CP_BLIT_0_OP(enum cp_blit_cmd val)1956 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1957 {
1958 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1959 }
1960
1961 #define REG_CP_BLIT_1 0x00000001
1962 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1963 #define CP_BLIT_1_SRC_X1__SHIFT 0
CP_BLIT_1_SRC_X1(uint32_t val)1964 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1965 {
1966 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1967 }
1968 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1969 #define CP_BLIT_1_SRC_Y1__SHIFT 16
CP_BLIT_1_SRC_Y1(uint32_t val)1970 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1971 {
1972 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1973 }
1974
1975 #define REG_CP_BLIT_2 0x00000002
1976 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1977 #define CP_BLIT_2_SRC_X2__SHIFT 0
CP_BLIT_2_SRC_X2(uint32_t val)1978 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1979 {
1980 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1981 }
1982 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1983 #define CP_BLIT_2_SRC_Y2__SHIFT 16
CP_BLIT_2_SRC_Y2(uint32_t val)1984 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1985 {
1986 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1987 }
1988
1989 #define REG_CP_BLIT_3 0x00000003
1990 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1991 #define CP_BLIT_3_DST_X1__SHIFT 0
CP_BLIT_3_DST_X1(uint32_t val)1992 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1993 {
1994 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1995 }
1996 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1997 #define CP_BLIT_3_DST_Y1__SHIFT 16
CP_BLIT_3_DST_Y1(uint32_t val)1998 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1999 {
2000 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
2001 }
2002
2003 #define REG_CP_BLIT_4 0x00000004
2004 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
2005 #define CP_BLIT_4_DST_X2__SHIFT 0
CP_BLIT_4_DST_X2(uint32_t val)2006 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
2007 {
2008 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
2009 }
2010 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
2011 #define CP_BLIT_4_DST_Y2__SHIFT 16
CP_BLIT_4_DST_Y2(uint32_t val)2012 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
2013 {
2014 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
2015 }
2016
2017 #define REG_CP_EXEC_CS_0 0x00000000
2018
2019 #define REG_CP_EXEC_CS_1 0x00000001
2020 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
2021 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
CP_EXEC_CS_1_NGROUPS_X(uint32_t val)2022 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
2023 {
2024 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
2025 }
2026
2027 #define REG_CP_EXEC_CS_2 0x00000002
2028 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
2029 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)2030 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
2031 {
2032 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
2033 }
2034
2035 #define REG_CP_EXEC_CS_3 0x00000003
2036 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
2037 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)2038 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
2039 {
2040 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
2041 }
2042
2043 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
2044
2045
2046 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2047 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
2048 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)2049 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
2050 {
2051 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
2052 }
2053
2054 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2055 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
2056 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)2057 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
2058 {
2059 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
2060 }
2061 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
2062 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)2063 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
2064 {
2065 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
2066 }
2067 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
2068 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)2069 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
2070 {
2071 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
2072 }
2073
2074
2075 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2076 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
2077 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)2078 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
2079 {
2080 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
2081 }
2082
2083 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2084 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
2085 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)2086 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
2087 {
2088 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
2089 }
2090
2091 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
2092 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
2093 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)2094 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
2095 {
2096 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
2097 }
2098 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
2099 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)2100 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
2101 {
2102 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
2103 }
2104 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
2105 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)2106 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
2107 {
2108 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
2109 }
2110
2111 #define REG_A6XX_CP_SET_MARKER_0 0x00000000
2112 #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
2113 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)2114 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
2115 {
2116 return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
2117 }
2118 #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
2119 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)2120 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)
2121 {
2122 return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
2123 }
2124
REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0)2125 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2126
REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0)2127 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2128 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
2129 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)2130 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
2131 {
2132 return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2133 }
2134
REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0)2135 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2136 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
2137 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)2138 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2139 {
2140 return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2141 }
2142
REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0)2143 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2144 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
2145 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)2146 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2147 {
2148 return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2149 }
2150
2151 #define REG_A6XX_CP_REG_TEST_0 0x00000000
2152 #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
2153 #define A6XX_CP_REG_TEST_0_REG__SHIFT 0
A6XX_CP_REG_TEST_0_REG(uint32_t val)2154 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
2155 {
2156 return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
2157 }
2158 #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
2159 #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20
A6XX_CP_REG_TEST_0_BIT(uint32_t val)2160 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2161 {
2162 return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2163 }
2164 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000
2165
2166 #define REG_CP_COND_REG_EXEC_0 0x00000000
2167 #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
2168 #define CP_COND_REG_EXEC_0_REG0__SHIFT 0
CP_COND_REG_EXEC_0_REG0(uint32_t val)2169 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2170 {
2171 return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2172 }
2173 #define CP_COND_REG_EXEC_0_BINNING 0x02000000
2174 #define CP_COND_REG_EXEC_0_GMEM 0x04000000
2175 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
2176 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
2177 #define CP_COND_REG_EXEC_0_MODE__SHIFT 28
CP_COND_REG_EXEC_0_MODE(enum compare_mode val)2178 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2179 {
2180 return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2181 }
2182
2183 #define REG_CP_COND_REG_EXEC_1 0x00000001
2184 #define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff
2185 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
CP_COND_REG_EXEC_1_DWORDS(uint32_t val)2186 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2187 {
2188 return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
2189 }
2190
2191 #define REG_CP_COND_EXEC_0 0x00000000
2192 #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
2193 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
CP_COND_EXEC_0_ADDR0_LO(uint32_t val)2194 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2195 {
2196 return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2197 }
2198
2199 #define REG_CP_COND_EXEC_1 0x00000001
2200 #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
2201 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
CP_COND_EXEC_1_ADDR0_HI(uint32_t val)2202 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2203 {
2204 return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2205 }
2206
2207 #define REG_CP_COND_EXEC_2 0x00000002
2208 #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
2209 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
CP_COND_EXEC_2_ADDR1_LO(uint32_t val)2210 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2211 {
2212 return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2213 }
2214
2215 #define REG_CP_COND_EXEC_3 0x00000003
2216 #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
2217 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
CP_COND_EXEC_3_ADDR1_HI(uint32_t val)2218 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2219 {
2220 return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2221 }
2222
2223 #define REG_CP_COND_EXEC_4 0x00000004
2224 #define CP_COND_EXEC_4_REF__MASK 0xffffffff
2225 #define CP_COND_EXEC_4_REF__SHIFT 0
CP_COND_EXEC_4_REF(uint32_t val)2226 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2227 {
2228 return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2229 }
2230
2231 #define REG_CP_COND_EXEC_5 0x00000005
2232 #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
2233 #define CP_COND_EXEC_5_DWORDS__SHIFT 0
CP_COND_EXEC_5_DWORDS(uint32_t val)2234 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2235 {
2236 return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2237 }
2238
2239 #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
2240 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
2241 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)2242 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2243 {
2244 return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2245 }
2246
2247 #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
2248 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
2249 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)2250 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2251 {
2252 return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2253 }
2254
2255 #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
2256 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
2257 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)2258 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2259 {
2260 return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2261 }
2262 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
2263 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20
CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)2264 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2265 {
2266 return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2267 }
2268
2269 #define REG_CP_REG_WRITE_0 0x00000000
2270 #define CP_REG_WRITE_0_TRACKER__MASK 0x00000007
2271 #define CP_REG_WRITE_0_TRACKER__SHIFT 0
CP_REG_WRITE_0_TRACKER(enum reg_tracker val)2272 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2273 {
2274 return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2275 }
2276
2277 #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
2278 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
2279 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)2280 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2281 {
2282 return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2283 }
2284
2285 #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
2286 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
2287 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)2288 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2289 {
2290 return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2291 }
2292 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
2293 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16
CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)2294 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2295 {
2296 return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2297 }
2298
2299 #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
2300 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
2301 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)2302 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2303 {
2304 return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2305 }
2306
2307 #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
2308 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
2309 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0
CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)2310 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2311 {
2312 return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2313 }
2314
2315
2316 #endif /* ADRENO_PM4_XML */
2317