Searched refs:DMA_BUF_MEM_CTRL (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_drm_dpe.c | 319 writel(0x00000008, base + DPE_RCH_VG0_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
323 writel(0x00000008, base + DPE_RCH_VG1_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
327 writel(0x00000008, base + DPE_RCH_VG2_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
330 writel(0x00000008, base + DPE_RCH_G0_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
334 writel(0x00000008, base + DPE_RCH_G1_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
336 writel(0x00000008, base + DPE_RCH_D0_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
338 writel(0x00000008, base + DPE_RCH_D1_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
339 writel(0x00000008, base + DPE_RCH_D2_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
340 writel(0x00000008, base + DPE_RCH_D3_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
341 writel(0x00000008, base + DPE_WCH0_DMA_OFFSET + DMA_BUF_MEM_CTRL); in dpe_clk_enable()
[all …]
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| D | kirin_dpe_reg.h | 212 #define DMA_BUF_MEM_CTRL (0x0854) macro
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