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Searched refs:DPE_RCH_G0_SCL_OFFSET (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/hisilicon/kirin/
Dkirin_dpe_reg.h44 #define DPE_RCH_G0_SCL_OFFSET (0x38200) macro
Dkirin_drm_dpe.c328 writel(0x00000088, base + DPE_RCH_G0_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
329 writel(0x00000008, base + DPE_RCH_G0_SCL_OFFSET + SCF_LB_MEM_CTRL); in dpe_clk_enable()