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Searched refs:DP_AUX_CH_CTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dhandlers.c828 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) in trigger_aux_channel_interrupt()
831 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
834 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
837 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
2953 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
2955 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
2957 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
/drivers/gpu/drm/i915/display/
Dintel_dp.c1678 return DP_AUX_CH_CTL(aux_ch); in g4x_aux_ctl_reg()
1681 return DP_AUX_CH_CTL(AUX_CH_B); in g4x_aux_ctl_reg()
1710 return DP_AUX_CH_CTL(aux_ch); in ilk_aux_ctl_reg()
1717 return DP_AUX_CH_CTL(AUX_CH_A); in ilk_aux_ctl_reg()
1754 return DP_AUX_CH_CTL(aux_ch); in skl_aux_ctl_reg()
1757 return DP_AUX_CH_CTL(AUX_CH_A); in skl_aux_ctl_reg()
Dintel_display_power.c606 val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch)); in icl_tc_phy_aux_power_well_enable()
610 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); in icl_tc_phy_aux_power_well_enable()
/drivers/gpu/drm/i915/
Di915_reg.h5793 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) macro