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Searched refs:DP_SEC_GSP2_ENABLE (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h157 SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
240 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
431 uint8_t DP_SEC_GSP2_ENABLE; member
562 uint32_t DP_SEC_GSP2_ENABLE; member
Ddce_stream_encoder.c880 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in dce110_stream_encoder_update_dp_info_packets()
906 DP_SEC_GSP2_ENABLE, 0, in dce110_stream_encoder_stop_dp_info_packets()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h214 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
412 type DP_SEC_GSP2_ENABLE;\
Ddcn10_stream_encoder.c738 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in enc1_stream_encoder_update_dp_info_packets()
858 DP_SEC_GSP2_ENABLE, 0, in enc1_stream_encoder_stop_dp_info_packets()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.h131 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
Ddcn30_dio_stream_encoder.c454 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); in enc3_stream_encoder_update_dp_info_packets()