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Searched refs:DP_VID_STREAM_CNTL (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.h69 SRI(DP_VID_STREAM_CNTL, DP, id), \
102 SRI(DP_VID_STREAM_CNTL, DP, id), \
179 uint32_t DP_VID_STREAM_CNTL; member
Ddce_stream_encoder.h91 SRI(DP_VID_STREAM_CNTL, DP, id), \
161 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
162 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
665 uint32_t DP_VID_STREAM_CNTL; member
Ddce_stream_encoder.c935 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in dce110_stream_encoder_dp_blank()
941 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); in dce110_stream_encoder_dp_blank()
949 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce110_stream_encoder_dp_blank()
956 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in dce110_stream_encoder_dp_blank()
1029 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in dce110_stream_encoder_dp_unblank()
Ddce_link_encoder.c461 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
513 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_stream_encoder.c492 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); in enc2_stream_encoder_dp_unblank()
493 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc2_stream_encoder_dp_unblank()
524 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc2_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c890 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in enc1_stream_encoder_dp_blank()
897 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); in enc1_stream_encoder_dp_blank()
905 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in enc1_stream_encoder_dp_blank()
912 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
992 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); in enc1_stream_encoder_dp_unblank()
Ddcn10_link_encoder.h61 SRI(DP_VID_STREAM_CNTL, DP, id), \
102 uint32_t DP_VID_STREAM_CNTL; member
Ddcn10_stream_encoder.h89 SRI(DP_VID_STREAM_CNTL, DP, id), \
134 uint32_t DP_VID_STREAM_CNTL; member
Ddcn10_link_encoder.c393 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_link_encoder.h51 SRI(DP_VID_STREAM_CNTL, DP, id), \
Ddcn30_dio_stream_encoder.h93 SRI(DP_VID_STREAM_CNTL, DP, id), \