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Searched refs:DWB_OGAM_RAMA_END_CNTL1_G (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb.h94 SR(DWB_OGAM_RAMA_END_CNTL1_G),\
253 SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh),\
799 uint32_t DWB_OGAM_RAMA_END_CNTL1_G; member
Ddcn30_dwb_cm.c100 gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G); in dwb3_program_ogam_luta_settings()