1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/hwmon.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 #include <asm/amd_nb.h>
24 #include <asm/processor.h>
25
26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28 MODULE_LICENSE("GPL");
29
30 static bool force;
31 module_param(force, bool, 0444);
32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34 /* Provide lock for writing to NB_SMU_IND_ADDR */
35 static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39 #endif
40
41 /* CPUID function 0x80000001, ebx */
42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46 /* DRAM controller (PCI function 2) */
47 #define REG_DCT0_CONFIG_HIGH 0x094
48 #define DDR3_MODE BIT(8)
49
50 /* miscellaneous (PCI function 3) */
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
53
54 #define REG_REPORTED_TEMPERATURE 0xa4
55
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57 #define NB_CAP_HTC BIT(10)
58
59 /*
60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
61 * and REG_REPORTED_TEMPERATURE have been moved to
62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
64 */
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68 /* Common for Zen CPU families (Family 17h and 18h) */
69 #define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800
70
71 #define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4))
72 #define ZEN_CCD_TEMP_VALID BIT(11)
73 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
74
75 #define ZEN_CUR_TEMP_SHIFT 21
76 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
77 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
78
79 #define ZEN_SVI_BASE 0x0005A000
80
81 /* F17h thermal registers through SMN */
82 #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
83 #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
84 #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
85 #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
86
87 #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
88 #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */
89 #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */
90 #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
91
92 /* F19h thermal registers through SMN */
93 #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
94 #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
95
96 #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
97 #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
98
99 struct k10temp_data {
100 struct pci_dev *pdev;
101 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
102 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
103 int temp_offset;
104 u32 temp_adjust_mask;
105 u32 show_temp;
106 bool is_zen;
107 };
108
109 #define TCTL_BIT 0
110 #define TDIE_BIT 1
111 #define TCCD_BIT(x) ((x) + 2)
112
113 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
114 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
115
116 struct tctl_offset {
117 u8 model;
118 char const *id;
119 int offset;
120 };
121
122 static const struct tctl_offset tctl_offset_table[] = {
123 { 0x17, "AMD Ryzen 5 1600X", 20000 },
124 { 0x17, "AMD Ryzen 7 1700X", 20000 },
125 { 0x17, "AMD Ryzen 7 1800X", 20000 },
126 { 0x17, "AMD Ryzen 7 2700X", 10000 },
127 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
128 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
129 };
130
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)131 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
132 {
133 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
134 }
135
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)136 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
137 {
138 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
139 }
140
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)141 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
142 unsigned int base, int offset, u32 *val)
143 {
144 mutex_lock(&nb_smu_ind_mutex);
145 pci_bus_write_config_dword(pdev->bus, devfn,
146 base, offset);
147 pci_bus_read_config_dword(pdev->bus, devfn,
148 base + 4, val);
149 mutex_unlock(&nb_smu_ind_mutex);
150 }
151
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)152 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
153 {
154 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
155 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
156 }
157
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)158 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
159 {
160 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
161 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
162 }
163
read_tempreg_nb_zen(struct pci_dev * pdev,u32 * regval)164 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
165 {
166 amd_smn_read(amd_pci_dev_to_node_id(pdev),
167 ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
168 }
169
get_raw_temp(struct k10temp_data * data)170 static long get_raw_temp(struct k10temp_data *data)
171 {
172 u32 regval;
173 long temp;
174
175 data->read_tempreg(data->pdev, ®val);
176 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
177 if ((regval & data->temp_adjust_mask) ||
178 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
179 temp -= 49000;
180 return temp;
181 }
182
183 static const char *k10temp_temp_label[] = {
184 "Tctl",
185 "Tdie",
186 "Tccd1",
187 "Tccd2",
188 "Tccd3",
189 "Tccd4",
190 "Tccd5",
191 "Tccd6",
192 "Tccd7",
193 "Tccd8",
194 };
195
k10temp_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)196 static int k10temp_read_labels(struct device *dev,
197 enum hwmon_sensor_types type,
198 u32 attr, int channel, const char **str)
199 {
200 switch (type) {
201 case hwmon_temp:
202 *str = k10temp_temp_label[channel];
203 break;
204 default:
205 return -EOPNOTSUPP;
206 }
207 return 0;
208 }
209
k10temp_read_temp(struct device * dev,u32 attr,int channel,long * val)210 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
211 long *val)
212 {
213 struct k10temp_data *data = dev_get_drvdata(dev);
214 u32 regval;
215
216 switch (attr) {
217 case hwmon_temp_input:
218 switch (channel) {
219 case 0: /* Tctl */
220 *val = get_raw_temp(data);
221 if (*val < 0)
222 *val = 0;
223 break;
224 case 1: /* Tdie */
225 *val = get_raw_temp(data) - data->temp_offset;
226 if (*val < 0)
227 *val = 0;
228 break;
229 case 2 ... 9: /* Tccd{1-8} */
230 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
231 ZEN_CCD_TEMP(channel - 2), ®val);
232 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
233 break;
234 default:
235 return -EOPNOTSUPP;
236 }
237 break;
238 case hwmon_temp_max:
239 *val = 70 * 1000;
240 break;
241 case hwmon_temp_crit:
242 data->read_htcreg(data->pdev, ®val);
243 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
244 break;
245 case hwmon_temp_crit_hyst:
246 data->read_htcreg(data->pdev, ®val);
247 *val = (((regval >> 16) & 0x7f)
248 - ((regval >> 24) & 0xf)) * 500 + 52000;
249 break;
250 default:
251 return -EOPNOTSUPP;
252 }
253 return 0;
254 }
255
k10temp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)256 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
257 u32 attr, int channel, long *val)
258 {
259 switch (type) {
260 case hwmon_temp:
261 return k10temp_read_temp(dev, attr, channel, val);
262 default:
263 return -EOPNOTSUPP;
264 }
265 }
266
k10temp_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)267 static umode_t k10temp_is_visible(const void *_data,
268 enum hwmon_sensor_types type,
269 u32 attr, int channel)
270 {
271 const struct k10temp_data *data = _data;
272 struct pci_dev *pdev = data->pdev;
273 u32 reg;
274
275 switch (type) {
276 case hwmon_temp:
277 switch (attr) {
278 case hwmon_temp_input:
279 if (!HAVE_TEMP(data, channel))
280 return 0;
281 break;
282 case hwmon_temp_max:
283 if (channel || data->is_zen)
284 return 0;
285 break;
286 case hwmon_temp_crit:
287 case hwmon_temp_crit_hyst:
288 if (channel || !data->read_htcreg)
289 return 0;
290
291 pci_read_config_dword(pdev,
292 REG_NORTHBRIDGE_CAPABILITIES,
293 ®);
294 if (!(reg & NB_CAP_HTC))
295 return 0;
296
297 data->read_htcreg(data->pdev, ®);
298 if (!(reg & HTC_ENABLE))
299 return 0;
300 break;
301 case hwmon_temp_label:
302 /* Show temperature labels only on Zen CPUs */
303 if (!data->is_zen || !HAVE_TEMP(data, channel))
304 return 0;
305 break;
306 default:
307 return 0;
308 }
309 break;
310 default:
311 return 0;
312 }
313 return 0444;
314 }
315
has_erratum_319(struct pci_dev * pdev)316 static bool has_erratum_319(struct pci_dev *pdev)
317 {
318 u32 pkg_type, reg_dram_cfg;
319
320 if (boot_cpu_data.x86 != 0x10)
321 return false;
322
323 /*
324 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
325 * may be unreliable.
326 */
327 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
328 if (pkg_type == CPUID_PKGTYPE_F)
329 return true;
330 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
331 return false;
332
333 /* DDR3 memory implies socket AM3, which is good */
334 pci_bus_read_config_dword(pdev->bus,
335 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
336 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
337 if (reg_dram_cfg & DDR3_MODE)
338 return false;
339
340 /*
341 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
342 * memory. We blacklist all the cores which do exist in socket AM2+
343 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
344 * and AM3 formats, but that's the best we can do.
345 */
346 return boot_cpu_data.x86_model < 4 ||
347 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
348 }
349
350 static const struct hwmon_channel_info *k10temp_info[] = {
351 HWMON_CHANNEL_INFO(temp,
352 HWMON_T_INPUT | HWMON_T_MAX |
353 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
354 HWMON_T_LABEL,
355 HWMON_T_INPUT | HWMON_T_LABEL,
356 HWMON_T_INPUT | HWMON_T_LABEL,
357 HWMON_T_INPUT | HWMON_T_LABEL,
358 HWMON_T_INPUT | HWMON_T_LABEL,
359 HWMON_T_INPUT | HWMON_T_LABEL,
360 HWMON_T_INPUT | HWMON_T_LABEL,
361 HWMON_T_INPUT | HWMON_T_LABEL,
362 HWMON_T_INPUT | HWMON_T_LABEL,
363 HWMON_T_INPUT | HWMON_T_LABEL),
364 HWMON_CHANNEL_INFO(in,
365 HWMON_I_INPUT | HWMON_I_LABEL,
366 HWMON_I_INPUT | HWMON_I_LABEL),
367 HWMON_CHANNEL_INFO(curr,
368 HWMON_C_INPUT | HWMON_C_LABEL,
369 HWMON_C_INPUT | HWMON_C_LABEL),
370 NULL
371 };
372
373 static const struct hwmon_ops k10temp_hwmon_ops = {
374 .is_visible = k10temp_is_visible,
375 .read = k10temp_read,
376 .read_string = k10temp_read_labels,
377 };
378
379 static const struct hwmon_chip_info k10temp_chip_info = {
380 .ops = &k10temp_hwmon_ops,
381 .info = k10temp_info,
382 };
383
k10temp_get_ccd_support(struct pci_dev * pdev,struct k10temp_data * data,int limit)384 static void k10temp_get_ccd_support(struct pci_dev *pdev,
385 struct k10temp_data *data, int limit)
386 {
387 u32 regval;
388 int i;
389
390 for (i = 0; i < limit; i++) {
391 amd_smn_read(amd_pci_dev_to_node_id(pdev),
392 ZEN_CCD_TEMP(i), ®val);
393 if (regval & ZEN_CCD_TEMP_VALID)
394 data->show_temp |= BIT(TCCD_BIT(i));
395 }
396 }
397
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)398 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
399 {
400 int unreliable = has_erratum_319(pdev);
401 struct device *dev = &pdev->dev;
402 struct k10temp_data *data;
403 struct device *hwmon_dev;
404 int i;
405
406 if (unreliable) {
407 if (!force) {
408 dev_err(dev,
409 "unreliable CPU thermal sensor; monitoring disabled\n");
410 return -ENODEV;
411 }
412 dev_warn(dev,
413 "unreliable CPU thermal sensor; check erratum 319\n");
414 }
415
416 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
417 if (!data)
418 return -ENOMEM;
419
420 data->pdev = pdev;
421 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
422
423 if (boot_cpu_data.x86 == 0x15 &&
424 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
425 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
426 data->read_htcreg = read_htcreg_nb_f15;
427 data->read_tempreg = read_tempreg_nb_f15;
428 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
429 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
430 data->read_tempreg = read_tempreg_nb_zen;
431 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
432 data->is_zen = true;
433
434 switch (boot_cpu_data.x86_model) {
435 case 0x1: /* Zen */
436 case 0x8: /* Zen+ */
437 case 0x11: /* Zen APU */
438 case 0x18: /* Zen+ APU */
439 k10temp_get_ccd_support(pdev, data, 4);
440 break;
441 case 0x31: /* Zen2 Threadripper */
442 case 0x71: /* Zen2 */
443 k10temp_get_ccd_support(pdev, data, 8);
444 break;
445 }
446 } else if (boot_cpu_data.x86 == 0x19) {
447 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
448 data->read_tempreg = read_tempreg_nb_zen;
449 data->show_temp |= BIT(TDIE_BIT);
450 data->is_zen = true;
451
452 switch (boot_cpu_data.x86_model) {
453 case 0x0 ... 0x1: /* Zen3 */
454 k10temp_get_ccd_support(pdev, data, 8);
455 break;
456 }
457 } else {
458 data->read_htcreg = read_htcreg_pci;
459 data->read_tempreg = read_tempreg_pci;
460 }
461
462 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
463 const struct tctl_offset *entry = &tctl_offset_table[i];
464
465 if (boot_cpu_data.x86 == entry->model &&
466 strstr(boot_cpu_data.x86_model_id, entry->id)) {
467 data->temp_offset = entry->offset;
468 break;
469 }
470 }
471
472 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
473 &k10temp_chip_info,
474 NULL);
475 return PTR_ERR_OR_ZERO(hwmon_dev);
476 }
477
478 static const struct pci_device_id k10temp_id_table[] = {
479 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
480 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
481 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
485 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
487 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
488 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
489 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
490 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
491 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
492 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
493 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
494 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
495 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
496 {}
497 };
498 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
499
500 static struct pci_driver k10temp_driver = {
501 .name = "k10temp",
502 .id_table = k10temp_id_table,
503 .probe = k10temp_probe,
504 };
505
506 module_pci_driver(k10temp_driver);
507