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Searched refs:FME_PWR_FPGA_LIMIT (Results 1 – 1 of 1) sorted by relevance

/drivers/fpga/
Ddfl-fme-main.c372 #define FME_PWR_FPGA_LIMIT 0x20 macro
502 v = readq(feature->ioaddr + FME_PWR_FPGA_LIMIT); in power1_fpga_limit_show()